Array size: 3 x 3 logic blocks.

Routing:

Net 0 (s27_in_2_)

SOURCE (2,0)  Pad: 1  
  OPIN (2,0)  Pad: 1  
 CHANX (2,0)  Track: 0  
 CHANY (1,1)  Track: 0  
  IPIN (2,1)  Pin: 1  
  SINK (2,1)  Class: 0  
 CHANY (1,1)  Track: 0  
 CHANY (1,2)  Track: 0  
  IPIN (2,2)  Pin: 1  
  SINK (2,2)  Class: 0  


Net 1 (s27_in_1_)

SOURCE (4,2)  Pad: 0  
  OPIN (4,2)  Pad: 0  
 CHANY (3,2)  Track: 1  
  IPIN (3,2)  Pin: 3  
  SINK (3,2)  Class: 0  


Net 2 (s27_in_3_)

SOURCE (3,0)  Pad: 0  
  OPIN (3,0)  Pad: 0  
 CHANX (3,0)  Track: 0  
 CHANY (3,1)  Track: 0  
 CHANY (3,2)  Track: 0  
 CHANX (3,2)  Track: 0  
 CHANX (2,2)  Track: 0  
 CHANX (1,2)  Track: 0  
 CHANY (0,2)  Track: 0  
 CHANY (0,1)  Track: 0  
 CHANX (1,0)  Track: 0  
  IPIN (1,1)  Pin: 0  
  SINK (1,1)  Class: 0  
 CHANX (1,2)  Track: 0  
  IPIN (1,2)  Pin: 2  
  SINK (1,2)  Class: 0  
 CHANX (3,2)  Track: 0  
  IPIN (3,2)  Pin: 2  
  SINK (3,2)  Class: 0  
 CHANX (3,0)  Track: 0  
  IPIN (3,1)  Pin: 0  
  SINK (3,1)  Class: 0  


Net 3 (s27_in_0_)

SOURCE (2,0)  Pad: 0  
  OPIN (2,0)  Pad: 0  
 CHANX (2,0)  Track: 1  
  IPIN (2,1)  Pin: 0  
  SINK (2,1)  Class: 0  


Net 4 (clock): global net connecting:

Block clock (#4) at (0, 2), Pin class -1.
Block n_n40 (#7) at (3, 2), Pin class 2.
Block n_n41 (#8) at (3, 1), Pin class 2.
Block n_n42 (#9) at (1, 2), Pin class 2.


Net 5 (s27_out)

SOURCE (1,1)  Class: 1  
  OPIN (1,1)  Pin: 4  
 CHANX (1,0)  Track: 1  
  IPIN (1,0)  Pad: 0  
  SINK (1,0)  Pad: 0  


Net 6 (n_n41)

SOURCE (3,1)  Class: 1  
  OPIN (3,1)  Pin: 4  
 CHANX (3,0)  Track: 1  
 CHANY (2,1)  Track: 1  
  IPIN (2,1)  Pin: 3  
  SINK (2,1)  Class: 0  
 CHANY (2,1)  Track: 1  
 CHANY (2,2)  Track: 1  
 CHANX (2,2)  Track: 1  
 CHANX (1,2)  Track: 1  
 CHANY (0,2)  Track: 1  
 CHANY (0,1)  Track: 1  
  IPIN (1,1)  Pin: 1  
  SINK (1,1)  Class: 0  
 CHANY (2,2)  Track: 1  
  IPIN (2,2)  Pin: 3  
  SINK (2,2)  Class: 0  


Net 7 (n_n42)

SOURCE (1,2)  Class: 1  
  OPIN (1,2)  Pin: 4  
 CHANX (1,1)  Track: 1  
 CHANY (1,1)  Track: 1  
  IPIN (1,1)  Pin: 3  
  SINK (1,1)  Class: 0  
  OPIN (1,2)  Pin: 4  
 CHANY (1,2)  Track: 1  
  IPIN (1,2)  Pin: 3  
  SINK (1,2)  Class: 0  


Net 8 ([13])

SOURCE (2,1)  Class: 1  
  OPIN (2,1)  Pin: 4  
 CHANY (2,1)  Track: 0  
 CHANX (2,1)  Track: 0  
 CHANX (1,1)  Track: 0  
  IPIN (1,1)  Pin: 2  
  SINK (1,1)  Class: 0  
 CHANX (1,1)  Track: 0  
  IPIN (1,2)  Pin: 0  
  SINK (1,2)  Class: 0  
 CHANY (2,1)  Track: 0  
 CHANX (3,1)  Track: 0  
  IPIN (3,2)  Pin: 0  
  SINK (3,2)  Class: 0  
 CHANY (2,1)  Track: 0  
  IPIN (3,1)  Pin: 1  
  SINK (3,1)  Class: 0  


Net 9 ([11])

SOURCE (2,2)  Class: 1  
  OPIN (2,2)  Pin: 4  
 CHANY (2,2)  Track: 0  
  IPIN (3,2)  Pin: 1  
  SINK (3,2)  Class: 0  


Net 10 (n_n40)

SOURCE (3,2)  Class: 1  
  OPIN (3,2)  Pin: 4  
 CHANX (3,1)  Track: 1  
 CHANX (2,1)  Track: 1  
  IPIN (2,1)  Pin: 2  
  SINK (2,1)  Class: 0  
 CHANX (2,1)  Track: 1  
  IPIN (2,2)  Pin: 0  
  SINK (2,2)  Class: 0  
