 | Dipl.-Inform. Julian Oppermann | ||
|---|---|---|---|
| Technische Universität Darmstadt | |||
| FB20 (Informatik) | |||
| FG Eingebettete Systeme und ihre Anwendungen | |||
| Hochschulstr. 10 | |||
| D-64289 Darmstadt | |||
| Telefon: +49 6151 / 16-22432 | |||
| E-Mail: | <nachname>@esa.tu-darmstadt.de | ||
| S2|02 (Piloty-Gebäude), Raum E121 | |||
| Sprechstunde: bitte Termin per Mail ausmachen | |||
Publikationen
Profil auf ResearchGateJulian Oppermann, Melanie Reuter-Oppermann, Lukas Sommer, Andreas Koch, Oliver Sinnen
Exact and Practical Modulo Scheduling for High-level Synthesis
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Accepted, currently in production Lukas Sommer, Julian Oppermann, Alejandro Molina, Carsten Binnig, Kristian Kersting, Andreas Koch
Automatic Mapping of the Sum-Product Network Inference Problem to FPGA-based Accelerators
IEEE International Conference on Computer Design (ICCD), Orlando, FL, USA, 10-2018
Paper ICCD 2018
Julian Oppermann, Sebastian Vollbrecht, Melanie Reuter-Oppermann, Oliver Sinnen, Andreas KochWork in Progress: GeMS: A Generator for Modulo Scheduling Problems
Intl. Conf. on Compilers, Architectures and Synthesis For Embedded Systems (CASES), ESWEEK, Torino, IT, 09-2018
Paper CASES 2018
Julian Oppermann, Melanie Reuter-Oppermann, Lukas Sommer, Oliver Sinnen, Andreas KochDependence Graph Preprocessing for Faster Exact Modulo Scheduling in High-level Synthesis
Intl. Conf. on Field Programmable Logic and Applications (FPL), Dublin, Ireland, 08-2018
Paper FPL 2018
Patrick Sittel, Martin Kumm, Julian Oppermann, Konrad Möller, Peter Zipf, Andreas KochILP-based Modulo Scheduling and Binding for Register Minimization
Intl. Conf. on Field Programmable Logic and Applications (FPL), Dublin, Ireland, 08-2018
Paper FPL 2018
Lukas Sommer, Julian Oppermann, Alejandro Molina, Carsten Binnig, Kristian Kersting, Andreas KochAutomatic Synthesis of FPGA-based Accelerators for the Sum-Product Network Inference Problem
ICML 2018 Workshop on Tractable Probabilistic Models (TPM), Stockholm, Sweden, 07-2018
Paper TPM 2018
Patrick Sittel, Julian Oppermann, Martin Kumm, Andreas Koch, Peter ZipfHatScheT: A Contribution to Agile HLS
FPGAs for Software Programmers (FSP), Dublin, Ireland, 08-2018
Paper FSP 2018
Robin Kruppe, Julian Oppermann, Andreas KochSupporting the RISC-V Vector Extensions in LLVM
2018 European LLVM Developers Meeting, Bristol, UK, 04-2018
Abstract Slides Video
Lukas Sommer, Julian Oppermann, Jens Korinth, Andreas KochOffloading OpenMP Target Regions to FPGA Accelerators Using LLVM
2018 European LLVM Developers Meeting, Bristol, UK, 04-2018
Paper OpenMP Offloading EuroLLVM 2018
Tobias Vincon, Sergey Haddock, Christian Riegger, Julian Oppermann, Andreas Koch, Ilia PetrovNoFTL-KV: Tackling Write-Amplification on KV-Stores with Native Storage Management
Proc. of the 21st International Conference on Extending Database Technology (EDBT), 03-2018
Paper EDBT 2018
Björn Liebig, Julian Oppermann, Oliver Sinnen, Andreas KochImproved High-Level Synthesis for Complex CellML Models
Proc. 14th International Symposium on Applied Reconfigurable Computing (ARC), Santorini (Greece), 05-2018
Paper ARC 2018 (preprint)
Lukas Sommer, Julian Oppermann, Jaco Hofmann, Andreas KochSynthesis of Interleaved Multithreaded Accelerators from OpenMP Loops
2017 International Conference on Reconfigurable Computing and FPGAs (ReConFig'17), Cancun (Mexico), 12-2017
Paper OpenMP ReConfig 2017 (preprint)
Julian Oppermann, Lukas Sommer, Andreas Koch SpExSim: assessing kernel suitability for C-based high-level hardware synthesis
Journal of Supercomputing, 07-2017
SpringerLink
Lukas Sommer, Julian Oppermann, Andreas KochC-based Synthesis of Area-Efficient Accelerators for OpenMP Worksharing Loops
Second International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC), Salt Lake City, UT (USA), 11-2016
Extended Abstract H2RC 2016
Julian Oppermann, Andreas Koch, Melanie Reuter-Oppermann, Oliver SinnenILP-based Modulo Scheduling for High-level Synthesis
International Conference on Compilers, Architectures and Synthesis For Embedded Systems (CASES), ESWEEK, Pittsburgh, PA (USA), 10-2016
Paper CASES 2016 ACM Digital Library
Julian Oppermann, Andreas KochDetecting Kernels Suitable for C-based High-Level Hardware Synthesis
2nd International Workshop on Reengineering for Parallelism in Heterogeneous Parallel Platforms (RePara), IEEE ScalCom, Toulouse (FR), 07-2016
Paper RePara 2016
Julian Oppermann, Andreas Koch, Ting Yu, Oliver SinnenDomain-specific Optimisation for the High-level Synthesis of CellML-based Simulation Accelerators
IEEE Proc. Intl. Conf. on Field Programmable Logic and Applications (FPL), London (UK), 09-2015
Paper FPL 2015
Ting Yu, Julian Oppermann, Chris Bradley, Oliver SinnenPerformance optimisation strategies for automatically generated FPGA accelerators for biomedical models
Concurrency and Computation: Practice and Experience, Wiley, Volume 28, Issue 5
Publisher
Jens Huthmann, Julian Oppermann, Andreas KochAutomatic high-level synthesis of multi-threaded hardware accelerators
IEEE Proc. Intl. Conf. on Field Programmable Logic and Applications (FPL), Munich (DE), 09-2014
Paper FPL 2014
Huthmann, J., Liebig, B., Oppermann, J., Koch, A. Hardware/software co-compilation with the Nymble system
in Proc. of the Intl. Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), Darmstadt, 2013
Paper ReCoSoC 2013