![]() | Lukas Sommer | ||
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Technische Universität Darmstadt | |||
FB20 (Informatik) | |||
FG Eingebettete Systeme und ihre Anwendungen | |||
Hochschulstr. 10 | |||
D-64289 Darmstadt | |||
Telefon: | +49 6151 / 16-22429 | ||
Fax: | +49 6151 / 16-22422 | ||
E-Mail: | sommer "at" esa.tu-darmstadt.de | ||
PGP Key: | link | ||
S2/02 (Piloty-Gebäude), Raum E121 |
Forschungsgebiete
- High-Level Synthese für FGPA-basierte Hardwarebeschleuniger
- Nebenläufige Hardware-Architekturen
- Hardware-Software-Co-Execution
Lebenslauf
- 2011-2014
- Studium Informatik, Bachelor of Science, TU Darmstadt
- 2014-2016
- Studium Informatik, Master of Science, TU Darmstadt
- seit 2016
- Wissenschaftlicher Mitarbeiter am Fachgebiet Eingebettete Systeme und ihre Anwendungen (ESA)
Veröffentlichungen
Lukas Sommer, Florian Stock, Leonardo Solis-Vasquez, Andreas KochEPHoS: Evaluation of Programming Models for Heterogeneous Systems
FAT Schriftenreihe 317, Forschungsvereinigung Automobiltechnik, 2019

Exact and Practical Modulo Scheduling for High-level Synthesis
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Accepted, currently in production Michael Halkenhäuser, Lukas Sommer
An alternative OpenMP Backend for Polly
2019 European LLVM Developers Meeting, Brussels, BE, 04-2019

Extending LLVM for Lightweight SPMD Vectorization: Using SIMD and Vector Instructions Easily from Any Language
2019 International Symposium on Code Generation and Optimization, Washington, D.C., US, 02-2019

Automatic Mapping of the Sum-Product Network Inference Problem to FPGA-based Accelerators
IEEE International Conference on Computer Design (ICCD), Orlando, FL, USA, 10-2018

Dependence Graph Preprocessing for Faster Exact Modulo Scheduling in High-level Synthesis
Intl. Conf. on Field Programmable Logic and Applications (FPL), Dublin, Ireland, 08-2018

Automatic Synthesis of FPGA-based Accelerators for the Sum-Product Network Inference Problem
ICML 2018 Workshop on Tractable Probabilistic Models (TPM), Stockholm, Sweden, 07-2018

Offloading OpenMP Target Regions to FPGA Accelerators Using LLVM
2018 European LLVM Developers Meeting, Bristol, UK, 04-2018

Synthesis of Interleaved Multithreaded Accelerators from OpenMP Loops
2017 International Conference on Reconfigurable Computing and FPGAs (ReConFig'17), Cancun (Mexico), 12-2017

OpenMP Device Offloading to FPGA Accelerators
International Conference on Application-specific Systems, Architectures and Processors (ASAP), Seattle (USA), 07-2017


SpExSim: assessing kernel suitability for C-based high-level hardware synthesis
Journal of Supercomputing, 07-2017

C-based Synthesis of Area-Efficient Accelerators for OpenMP Worksharing Loops
Second International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC), Salt Lake City, UT (USA), 11-2016
