Writing your thesis in the ESA group

Thank you for your interest in writing a thesis in our group. In general, we have the two major research areas Computer Architecture/Hardware Design and Programming Tools.

For the first, we expect you not only to have successfully completed the mandatory courses Digital Design (DT/LE), Computer Organization (RO/RS1), and Architecture and Design of Computing Systems (AER). You should also have completed the two Embedded Systems Hands-On Labs (ESHO1/2) to gain practical experience in actually working with the hardware and the design tools.

If you are interested in a thesis in the area of Programming Tools, we expect you to have successfully completed the mandatory course Introductory Compiler Construction (EiCB/C1) and elective one Advanced Compiler Construction (C2). Ideally, you have also passed Practical FPGA Programming in High-Level Languages (FPGAHLL).

If you intend to focus on low-level ASIC and FPGA design tools, successfully completing the lecture and labs in Algorithms for Chip Design (ACE) is required. None of these courses is a hard requirement, of course. If you obtained a solid level of competency in these fields in comparable courses (e.g., in other departments, or from other universities), talk to us! We will determine the best course of action for you.

To given you an idea what typical BSc/MSc topics in our group look like, consider the following list.

Please note that this list is only to give you an overview of potential thesis topics. Depending on your qualifications and interests, we might be able to find more suitable/interesting topics. Please refer to this list to find out the appropriate research assistant to contact.

Thesis Topics

  • Automatic Generation of TLM to pin-level adapters for SystemC using a DSL

    Supervisor(s):
    Status: Taken

    SystemC is a library which facilitates event-driven simulation of concurrent processes written in C++. Tools like Verilator allow to generate the SystemC description for an existing hardware module written in a HDL (Verilog, VHDL). This in turn promises easy simulation of hardware modules as part of a larger SystemC model. However, bigger SystemC models often use Transaction-level Modeling (TLM) for communication between individual parts of the system while Verilator can only generate the interface based on the pins of the original HDL description. The goal in this thesis will be to create tools which can automatically generate adapters which can translate a TLM transaction into a series of signal transitions and vice versa. As this requires knowledge of the concrete protocol (e.g. AXI) a DSL will be used to describe the properties of the protocol. You will implement these tools, which use the protocol description provided via the DSL, to generate appropriate TLM to pin-level adapters for SystemC. Basic knowledge of SystemC and TLM can be helpful, but can also be acquired as a part of the thesis work.

    Requirements:
    • AER
    • EiCB
    Recommended:
    • ESHO 1
    • ESHO 2
    • C++

  • Automatic generation of randomized coreDSL descriptions and ML-based area estimation

    Supervisor(s):
    Status: Available

    CoreDSL is a domain specific language used to describe the Instruction Set Architecture (ISA) of processor cores. In addition to describing an entire ISA, only extensions (ISAX) may be described and later used to extend an already existing core. One tool developed at our group allows for automatic scheduling and hardware generation for such CoreDSL descriptions.

    Currently, this tool has been tested with a limited amount of ISAXes. Hence, in this thesis, you will create means to automatically generate syntactically correct CoreDSL files and test our tooling against them. We believe that this will help to uncover bugs and unaccounted edge-cases.

    For a masters thesis, you’ll additionally use chip design tools to find the area consumed by your generated ISAXes. With that information, you’ll design and implement a machine learning system that should be able to predict the required area for different scheduling solutions created from your ISAX description. As you’ll need a lot of input data to feed the machine learning algorithms, the automatic randomized generation will come in handy! As one ISAX may generate millions of possible scheduling solutions, your work will guide which of those solutions are selected and hence likely improve the quality of the resulting hardware module.

    Requirements:
    • Experience with Python
    Recommended:
    • Experience with C++ and ESHO 1 or ESHO 2

  • Branch Prediction Awareness for an IoT Security Monitoring Interface

    Supervisor(s):
    Status: Taken

    We are developing a tightly-integrated low-overhead on-chip security monitor for IoT-class single-issue in-order RISC-V cores with focus on Control Flow, Data Flow and Value Invariant Integrity. As part of this project, we have implemented an interface to forward tracing information of uncommitted instructions from 6 different RISC-V cores to our security monitor. As part of this thesis, you will recapture the existing implementation and extend the interface for branch prediction awareness. This will provide additional evaluation latency headroom to the security monitor and reduce the number of stalls for guaranteed attack prevention. You will extend the existing CI pipeline to cover your changes. Finally, you will evaluate the performance improvement.

    Requirements:
    • ESHO 2
    • Bluespec or similar HDL
    • CPU architectures
    Recommended:

  • Design of an improved extension board for ESHO1

    Supervisor(s):
    Status: Taken

    In our ESHO1 lab, students program an embedded system comprising a Raspberry Pi and custom extension board including several sensors. Over the years, we’ve noticed some drawbacks with the current extension board design. As part of this lab, you will design an improved version. The target design has:

    • ARM-M0 MCU
    • A variety of sensors connected via I2C, SPI, ADC or GPIO
    • User I/O (e.g. Buttons, Joysticks, LEDs, Buzzer)
    • Connectivity with Pi (e.g UART, SPI, I2C)
    • Extension headers
    • One wireless option

    A main challenge will be part selection and reduction of overall PCB cost. You will also implement a verification program to check for board defects.

    This topic is most suited for the 6/9CP practical lab.

    Requirements:
    • ESHO1
    • KiCad or similar program
    • C/C++
    Recommended:

  • Evaluation of cache implementations

    Supervisor(s):
    Status: Taken

    RISC-V is an open instruction set architecture enabling design, manufacturing and selling of processors without licensing fees. Since its conception, a plethora of processors has been proposed in academia and industry. RISC-V is especially interesting in education since the entire documentation is open source.

    At the Embedded Systems and Applications Group, we are developing a configurable RISC-V processor aimed at education. Our goal is to provide a legible, highly configurable processor which supports advanced concepts like out-of-order computation, speculation and multithreading. The processor still requires a cache implementation. Instead of writing our own cache, we want to reuse an existing implementation.

    Your task would consist of the following (non-exhaustive) steps:

    • Research of state-of-the-art cache implementations and extraction from open-source projects (e.g. RocketSoc)
    • Evaluation of the selected caches
    • Integration into our (multicore) RISC-V processor (written in BSV, cache may be another HDL)
    • Evaluation of the processor speedup
    Requirements:
    • Bluespec or other HDL
    Recommended:
    • ESHO 2

  • Hardware Accelerator for RISC-V code Path Fuzzing

    Supervisor(s):
    Status: Taken

    Code Fuzzing on a dedicated accelerator can be a lot faster than using a general purpose CPU. As part of this thesis you will implement a FPGA-based RISC-V code path fuzzer using our existing framework (TaPaSCo) and existing RISC-V cores. The Host will launch jobs, which are executed on the impendent RISC-V cores. These jobs contain the same application, but varying input parameters, resulting in different CF paths. Using a hash function, all taken paths will be traced and stored within the FPGA’s HBM. Interesting (new) paths will cause interrupts to inform the host and to adapt the following job’s parameters. When all jobs are finished, the results are transferred to the host.

    Requirements:
    • Bluespec or similar HDL
    Recommended:
    • ESHO 2

  • Implementing a Post-Quantum Cryptography Security Accelerator

    Supervisor(s):
    Status: Taken

    Our group works on small IoT (ASIC) designs as well as high performance FPGA accelerators. This thesis will be a cooperation with Quantum and Physical attack resistant Cryptography (QPC). While general purpose processors can run both common and quantum-proof cryptography algorithms, there are currently only few accelerators for the latter group. This includes accelerators for isogeny-based key cryptography. As part of this thesis, you will first do literature research and list existing implementations. Next, we will locate the most promising design trade-off (low area or high performance). Depending on this choice, your accelerator can be either standalone or tightly integrated into a RISC-V core. Finally, you will implement and evaluate the results.

    Requirements:
    • ESHO 2
    • Bluespec or similar HDL
    Recommended:
    • Math and Crypto skills
    • Hands-on TaPaSCo

  • Verification of an open-source speculative RISC-V processor

    Supervisor(s):
    Status: Taken

    RISC-V is an open instruction set architecture enabling design, manufacturing and selling of processors without licensing fees. Since its conception, a plethora of processors has been proposed in academia and industry.

    At the Embedded Systems and Applications Group, we are developing a UVM-framework for the lock-step verification of simple and complex RISC-V cores using Python. While the framework already provides the facilities to verify normal execution flow of in-order CPUs, it still requires mechanisms to facilitate verification of complex speculative multi-commit cores like OpenHW Group’s CVA5.

    Your task would consist of the following (non-exhaustive) steps:

    • Research of state-of-the-art methods for lock-step verification of complex CPUs, especially with respect to simple reference models
    • Extension of CVA5, in order to provide a verification interface to the framework
    • Implementation of one SotA-approach inside the framework
    • Evaluation of the verification approach on the extended CVA5
    Requirements:
    • Architekturen und Entwurf von Rechnersystemen
    • Good reading comprehension of SystemVerilog and basic SystemVerilog coding skills
    • Good Python and OOP skills
    • C++ OOP skills
    Recommended: