Writing your thesis in the ESA group

Thank you for your interest in writing a thesis in our group. In general, we have the two major research areas Computer Architecture/Hardware Design and Programming Tools.

For the first, we expect you not only to have successfully completed the mandatory courses Digital Design (DT/LE), Computer Organization (RO/RS1), and Architecture and Design of Computing Systems (AER). You should also have completed the two Embedded Systems Hands-On Labs (ESHO1/2) to gain practical experience in actually working with the hardware and the design tools.

If you are interested in a thesis in the area of Programming Tools, we expect you to have successfully completed the mandatory course Introductory Compiler Construction (EiCB/C1) and elective one Advanced Compiler Construction (C2). Ideally, you have also passed Practical FPGA Programming in High-Level Languages (FPGAHLL).

If you intend to focus on low-level ASIC and FPGA design tools, successfully completing the lecture and labs in Algorithms for Chip Design (ACE) is required. None of these courses is a hard requirement, of course. If you obtained a solid level of competency in these fields in comparable courses (e.g., in other departments, or from other universities), talk to us! We will determine the best course of action for you.

To given you an idea what typical BSc/MSc topics in our group look like, consider the following list.

Please note that this list is only to give you an overview of potential thesis topics. Depending on your qualifications and interests, we might be able to find more suitable/interesting topics. Please refer to this list to find out the appropriate research assistant to contact.

Thesis Topics

  • Automatic Generation of TLM to pin-level adapters for SystemC using a DSL

    Supervisor(s):
    Status: Not taken

    SystemC is a library which facilitates event-driven simulation of concurrent processes written in C++. Tools like Verilator allow to generate the SystemC description for an existing hardware module written in a HDL (Verilog, VHDL). This in turn promises easy simulation of hardware modules as part of a larger SystemC model. However, bigger SystemC models often use Transaction-level Modeling (TLM) for communication between individual parts of the system while Verilator can only generate the interface based on the pins of the original HDL description. The goal in this thesis will be to create tools which can automatically generate adapters which can translate a TLM transaction into a series of signal transitions and vice versa. As this requires knowledge of the concrete protocol (e.g. AXI) a DSL will be used to describe the properties of the protocol. You will implement these tools, which use the protocol description provided via the DSL, to generate appropriate TLM to pin-level adapters for SystemC. Basic knowledge of SystemC and TLM can be helpful, but can also be acquired as a part of the thesis work.

    Requirements:
    • AER
    • EiCB
    Recommended:
    • ESHO 1
    • ESHO 2
    • C++

  • Branch Prediction Awareness for an IoT Security Monitoring Interface

    Supervisor(s):
    Status: Taken

    We are developing a tightly-integrated low-overhead on-chip security monitor for IoT-class single-issue in-order RISC-V cores with focus on Control Flow, Data Flow and Value Invariant Integrity. As part of this project, we have implemented an interface to forward tracing information of uncommitted instructions from 6 different RISC-V cores to our security monitor. As part of this thesis, you will recapture the existing implementation and extend the interface for branch prediction awareness. This will provide additional evaluation latency headroom to the security monitor and reduce the number of stalls for guaranteed attack prevention. You will extend the existing CI pipeline to cover your changes. Finally, you will evaluate the performance improvement.

    Requirements:
    • ESHO 2
    • Bluespec or similar HDL
    • CPU architectures
    Recommended:

  • Design of a RISC-V ISA Extension to Accelerate Elliptic Curve Cryptography in IoT Devices

    Supervisor(s):
    Status: Taken

    The free and open RISC-V instruction set architecture (ISA) aims to enable innovation in a traditionally very proprietary and closed field, and currently receives a lot of attention in academia, as well as growing industry support. As part of the Scale4Edge project, the ESA group is developing a toolchain to integrate custom ISA extensions (ISAX), described in a high-level language, into RISC-V processor core suitable for IoT settings.

    The goal of this thesis is to design and evaluate an ISAX to bring elliptic curve cryptography (ECC) to IoT processors in an energy-efficient way. Subtasks include:

    • Getting familiar with ECC, and finding a suitable implementation in C to set up a demonstrator application
    • Analysis of performance bottlenecks
    • Specification of one (or more!) ISAX for ECC acceleration (defining instructions and their semantics)
    • Hardware implementation in a RISC-V core (either directly using SpinalHDL, or using ESA’s high-level flow when available)
    • Providing compiler support
    • Evaluation using an FPGA softcore

    The scope of this thesis may be tailored to either a B.Sc. or M.Sc. degree, and according to the candidate’s background and interests.

    Requirements:
    • RO/RS1
    • Basic familiarity with low-level software development (C, Makefiles, Linux, shell scripts, git, ...)
    Recommended:
    • Experience with compiler construction, high-level synthesis, FPGA design tools, possibly, but not necessarily from C2, FPGAHLL and ESHO1/2

  • Evaluating the performance of OpenCL-based task-parallel kernels from the PARSEC benchmark suite on FPGAs

    Supervisor(s):
    Status: Available

    OpenCL provides a high-level specification for heterogeneous computing systems. While it has been mainly used for highly-threaded devices such as GPUs, OpenCL has been also adopted for FPGAs in the last years. Porting applications onto GPUs and CPUs follows the typical data parallelization. However, to get reasonable performance on FPGAs, a different approach is required.

    In that regard, task parallelization is a suitable approach. Current FPGA tools provide means for inferring hardware constructions from high-level OpenCL abstractions. In addition, such tools support OpenCL pipes, i.e., on-chip FIFO-like structures for the purpose of transferring data between kernels running concurrent tasks. Despite that support, the performance of task-parallel OpenCL designs on FPGAs has not been extensively analyzed. The fact that most OpenCL-for-FPGAs studies focus on relatively simple patterns, leaves an understanding gap on designs with complex or irregular on-chip communication.

    The goal of this thesis is to explore parallelization possibilities, and to evaluate the efficiency of task-parallelization using OpenCL on FPGAs. This includes understanding the caveats, and finding suitable communication patterns. For that purpose, the PARSEC Benchmark Suite will be used as a case study. Subtasks include:

    • Getting familiar with OpenCL and corresponding tools for FPGAs
    • Getting familiar with PARSEC (https://parsec.cs.princeton.edu)
    • Selecting a suitable subset of cases from PARSEC for task parallelization
    • Porting the selected cases using OpenCL
    • Evaluating and optimizing their performance on FPGAs
    • Comparing results vs. corresponding implementations on other devices (https://dl.acm.org/doi/10.1145/2829952)

    The scope of this thesis may be tailored to either a B.Sc. or M.Sc. degree, based on the candidate’s background and interests.

    Requirements:
    • FPGAHLL
    • Familiarity with tools for software development (Makefiles, Linux, shell scripts, git, etc)
    Recommended:
    • Experience with parallel programming is a big plus, but not a requirement

  • FireSim on local FPGAs

    Supervisor(s):
    Status: Not taken

    FireSim is a high-performance simulator for hardware designs. For the acceleration of the simulation, it uses FPGAs from the public cloud (AWS EC2 F1). In this thesis you will implement an environment to run FireSim on various locally available FPGAs (e.g. Alveo U280). The work should utilize the portability features of our framework TaPaSCo.

    Requirements:
    • Architekturen und Entwurf von Rechnersystemen
    • ESHO 2
    Recommended:
    • Praktische FPGA-Programmierung mit Hochsprachen

  • Hardware Accelerator for RISC-V code Path Fuzzing

    Supervisor(s):
    Status: Taken

    Code Fuzzing on a dedicated accelerator can be a lot faster than using a general purpose CPU. As part of this thesis you will implement a FPGA-based RISC-V code path fuzzer using our existing framework (TaPaSCo) and existing RISC-V cores. The Host will launch jobs, which are executed on the impendent RISC-V cores. These jobs contain the same application, but varying input parameters, resulting in different CF paths. Using a hash function, all taken paths will be traced and stored within the FPGA’s HBM. Interesting (new) paths will cause interrupts to inform the host and to adapt the following job’s parameters. When all jobs are finished, the results are transferred to the host.

    Requirements:
    • Bluespec or similar HDL
    Recommended:
    • ESHO 2

  • Implementing a Post-Quantum Cryptography Security Accelerator

    Supervisor(s):
    Status: Taken

    Our group works on small IoT (ASIC) designs as well as high performance FPGA accelerators. This thesis will be a cooperation with Quantum and Physical attack resistant Cryptography (QPC). While general purpose processors can run both common and quantum-proof cryptography algorithms, there are currently only few accelerators for the latter group. This includes accelerators for isogeny-based key cryptography. As part of this thesis, you will first do literature research and list existing implementations. Next, we will locate the most promising design trade-off (low area or high performance). Depending on this choice, your accelerator can be either standalone or tightly integrated into a RISC-V core. Finally, you will implement and evaluate the results.

    Requirements:
    • ESHO 2
    • Bluespec or similar HDL
    Recommended:
    • Math and Crypto skills
    • Hands-on TaPaSCo

  • Improving Rapid Prototyping Techniques

    Supervisor(s):
    Status: Not taken

    One disadvantage when using FPGAs are long compilation runtimes. To overcome this, new implementation workflows emerge. One such example is solving the placement problem in a more modular manner. The corresponding workflow first implements each module of the design separately and in the end stitches, places and routes the complete design. The biggest advantage compared to the traditional EDA tools is a lower run-time after a design update. If only one module is modified, the workflow will re-implement it and then directly go to the stitching step. It does not need to re-implement the rest of the modules, which were not updated. This brings significant speed up compared to traditional tools that re-implement the whole design. However, the quality of results is not always comparable to the traditional tools. The thesis topic would focus on improving such algorithms.

    Requirements:
    • Architekturen und Entwurf von Rechnersystemen
    • Funktionale und objektorientierte Programmierkonzepte
    Recommended:
    • Algorithmen für Chip-Entwurfswerkzeuge

  • Optimizing OpenCL-based Molecular Docking on multi-core CPUs

    Supervisor(s):
    Status: Taken

    Molecular docking simulations are key methods in computer-aided drug design. From a computational perspective, a docking job consists of compute-intensive calculations that can profit a lot from hardware-based acceleration.

    Our group has been developing AutoDock-GPU, and OpenCL-accelerated molecular docking program that targets different computing platforms including GPUs and CPUs. While the same OpenCL code can run on different computer architectures, it is not performance portable.

    In this thesis, we seek to incorporate and evaluate CPU-specific code optimizations to fine-tune the performance of AutoDock-GPU on multi-core CPUs. Such optimization includes suitable code re-factoring in data types, memory layouts, workload distribution, and other relevant aspects.

    • Getting familiar with the OpenCL language and the optimization guidelines for multi-core CPUs
    • Getting familiar with the AutoDock-GPU application (https://github.com/ccsb-scripps/AutoDock-GPU)
    • Identifying the main bottlenecks of AutoDock-GPU on multi-core CPUs
    • Code refactoring for optimizing performance

    The scope of this thesis may be tailored to either a B.Sc. or M.Sc. degree, based on the candidate’s background and interests.

    Requirements:
    • Familiarity with C/C++-based parallel programming languages (OpenCL, CUDA, etc)
    • Familiarity with tools for software development (Makefiles, Linux, shell scripts, git, etc)
    Recommended:
    • Experience with software profiling

  • Porting and evaluating the Coral-2 AMG benchmark on modern Vector Machines

    Supervisor(s):
    Status: Taken

    A recently-released vector computing system is the NEC SX-Aurora. It aims to achieve high sustained performance by leveraging its up to 1.2 TB/s of memory bandwidth. In order to explore the programming and performance capabilitites of this vector machine, relevant benchmarks have to be evaluated.

    In this thesis, the AMG application from the Coral-2 Benchmarks will be used for that purpose. AMG consists of an algebraic multigrid solver for linear systems from problems on unstructured grids. Particularly, AMG is memory-access bound, a characteristic that makes it suitable for evaluating the sustained performance on SX-Aurora. Subtasks include:

    • Getting familiar with the NEC SX-Aurora vector machine (https://www.hpc.nec/documentation#preliminary-en)
    • Getting familiar with the Coral-2 AMG benchmark (https://asc.llnl.gov/coral-2-benchmarks)
    • Porting the Coral-2 AMG to the NEC SX-Aurora
    • Evaluating and optimizing performance
    • Comparing results vs. existing implementations on modern GPUs

    The scope of this thesis may be tailored to either a B.Sc. or M.Sc. degree, based on the candidate’s background and interests.

    Requirements:
    • C/C++ programming language
    • Familiarity with tools for software development (Makefiles, Linux, shell scripts, git, etc)
    Recommended:
    • Experience with parallel programming is a big plus, but not a requirement

  • TaPaSCo full-system simulation

    Supervisor(s):
    Status: Not taken

    Our group develops the framework TaPaSCo for creating FPGA designs. With the long development cycles in hardware development, a simulation could improve productivity of the developers. The goal of this thesis is to develop a simulation framework, which allows to simulate a complete TaPaSCo composition. Simulation should be possible at different complexity levels and could be as down to post-implementation simulation including memory models. For integration into the TaPaSCo software workflow, a device driver should provide accesses into the simulation.

    Requirements:
    • Architekturen und Entwurf von Rechnersystemen
    • ESHO 2
    Recommended: