While part of the Computer Science department, much of our work occurs at the level of the hardware-software interface. Our current research focus is on how to efficiently provide computing performance in situations where the capabilities of a standard microprocessor do not suffice, or its energy requirements would be excessive.

As an alternative, we propose adaptive computers: combining a smaller, low-power microprocessor with a highly optimized reconfigurable compute unit. The structure of the latter can then be optimally adapted to the precise needs of the current application, and thus provide the required compute power with reduced energy consumption.

To achieve this goal, we realize hardware demonstrators for such computer architectures (including the required operating system ports), and evaluate these using practical applications from a variety of fields. After very promising results, we have now concentrated on making the potential of such computers available even to developers who lack the skills in hardware design that are still required to program such systems. To this end, we have been working on a complete compile flow for partitioning a program in a software high-level programming language for separate execution on the two compute units. The part assigned to the reconfigurable compute unit is then processed further using techniques from hardware synthesis and physical chip design (mapping, placement, routing).

Many of our research efforts rely on support by motivated students with appropriate skills and experience. Thus, our group also develops lectures and labs on the wide range of topics listed above.


  • Two ESA papers get accepted at FPL 2022

    We are very happy to announce that two submitted papers of our group have been accepted for presentation at FPL 2022

    The first paper entitled DeLiBA: An Open-Source Hardware/Software Framework for the Development of Linux Block I/O Accelerators – by Babar Khan, Carsten Heinz, and Andreas Koch – is a result of the SODDAS project. DeLiBA aims to address Linux block I/O acceleration by allowing development of software components of the I/O stack in the user space instead of the kernel space, and leverages a proven FPGA SoC framework to quickly compose and deploy the actual FPGA-based I/O accelerators. The framework uses a software-defined distributed storage protocol, namely Ceph, for the proof-of-concept implementation.

    The second paper entitled Direct Device-to-Device Physical Page Migrations in Multi-FPGA Shared Virtual Memory Systems – by Torben Kalkhof and Andreas Koch – extends the TaPaSCo SVM feature by introducing Shared Virtual Memory (SVM) with physical page migrations to multi-FPGA architectures. Three different data transfer mechanisms for the additional direct device-to-device page migrations are examined in this work: a two-step copy approach via PCIe and a bounce buffer in host memory, direct PCIe endpoint-to-endpoint transfers, and data transfers over a 100G Ethernet connection.

    Congratulations and keep up the good work everyone!

    By Torben Kalkhof, 20.07.2022

  • ESA paper gets accepted at DAC 2022

    We are very happy to announce that our submitted paper has been accepted for presentation at DAC 2022.

    This paper entitled SCAIE-V: An Open-Source SCAlable Interface for ISA Extensions for RISC-V Processors –- by Mihaela Damian, Julian Oppermann, Christoph Spang and Andreas Koch -– is a result of the Scale4Edge project. The paper presents a new scalable interface named SCAIE-V, which integrates custom instructions into RISC-V cores. Currently, the project supports 4 cores (Piccolo, PicoRV32, VexRiscv and ORCA) for which the custom instructions can be integrated automatically. The interface can interact with the core’s register file, program counter as well as memory bus. The corresponding logic is added only if it is required by the custom instruction. Moreover, SCAIE-V supports decoupled instructions, which run in parallel to the main pipeline. All these features facilitate a faster integration of ISA extensions while reaching for a low hardware penalty.

    By Brindusa Mihaela Damian, 24.03.2022

  • Two ESA papers get accepted at FPT 2021

    We are very happy to announce that two submitted papers by our group have been accepted for presentation at FPT 2021.

    The first paper entitled Efficient Physical Page Migrations in Shared Virtual Memory Reconfigurable Computing Systems – by Torben Kalkhof and Andreas Koch – proposes an open-source development framework that provides Shared Virtual Memory with physical page migration capabilities to PCIe-attached FPGA-based cards. Based on the experiments, the performance of page migrations may even exceed that of conventional DMA copy-based accelerator operations by overlapping computations and migrations.

    The second paper entitled Scalable and Flexible High-Performance In-Network Processing of Hash Joins in Distributed Databases – by Johannes Wirth, Jaco A. Hofmann, Lasse Thostrup, Carsten Binnig, Andreas Koch – combines the usage of DDR-DRAM and HBM memories to implement an FPGA-based In-Network Hash Join accelerator. By doing so, larger joins are supported, as well as the far-faster and more-parallel HBM accesses can be leveraged. As a result, the accelerator achieves 3x higher performance compared to previous work, which was based on HBM only.

    Good work everyone!

    By Dr.-Ing. Leonardo Solis-Vasquez, 5.11.2021

  • Lukas Sommer defends his Ph.D.-thesis

    ​​On 18th October 2021, Lukas Sommer successfully defended his Ph.D.-thesis entitled Programming Heterogeneous Systems with General and Domain-Specific Frameworks. In his work, Lukas investigated general and domain-specific solutions to the challenges of heterogeneous systems programming.

    Lukas’ contributions comprise the identification of key factors to assess the suitability of general programming frameworks for applications and target platforms. Furthermore, he developed a domain-specific compiler for Sum-Product Networks (SPNs) that can target CPUs, GPUs, and FPGAs. The SPN programs produced by Lukas’ compiler can reach inference throughput of multiple orders of magnitude higher compared to existing Python-based libraries.

    Congratulations to Dr.-Ing. Lukas Sommer!

    By Dr.-Ing. Leonardo Solis-Vasquez, 20.10.2021

  • ESA contributes with article on AutoDock-GPU to HiPEAC info 64

    The latest issue of the HiPEAC Info magazine is out now! And it features an article about the latest developments of AutoDock-GPU, the GPU-accelerated molecular docking application we developed in collaboration with the ForliLab at Scripps Research.

    This article describes how AutoDock-GPU helps improving the processing speed of drug discovery simulations, as well as how the AutoDock-GPU’s code has been set to work on computers all over the globe, ranging from Rasberry Pis to servers equipped with high-end GPUs. This is thanks to the recent efforts by Scripps Research and the World Community Grid, which have enabled the use of AutoDock-GPU in the OpenPandemics: COVID-19 project.

    Enjoy reading the full HiPEAC info 64 magazine!

    By Dr.-Ing. Leonardo Solis-Vasquez, 18.10.2021

  • Two ESA papers get accepted at H2RC 2021

    We are very happy to announce that two submitted papers by our group have been accepted for presentation at H2RC 2021.

    The first paper entitled Near Data FPGA-Accelerated Processing of Collective and Inference Operations in Disaggregated Memory Systems – by Carsten Heinz and Andreas Koch – realizes an FPGA-based disaggregated system that extends distributed memory controllers with hardware-accelerated compute capabilities. This work provides a system capable of performing Near-Data Processing (NDP) operations, as well as an automated tool flow aimed for high usability of the proposed technology, even to users unfamiliar with hardware design.

    The second paper entitled Optimizing a Hardware Network Stack to Realize an In-Network ML Inference Application – by Marco Hartmann, Lukas Weber, Johannes Wirth, Lukas Sommer, and Andreas Koch — integrates into the open-source TaPaSCo framework, a high-throughput hardware network stack, which can operate at or close to theoretical performance in a network-attached machine learning inference appliance. Furthermore, this work provides a library of easy-to-use design primitives for network functionality, and thus, aims to facilitate the development of network-attached FPGA-based accelerators.

    Good work everyone!

    By Dr.-Ing. Leonardo Solis-Vasquez, 1.10.2021

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