While part of the Computer Science department, much of our work occurs at the level of the hardware-software interface. Our current research focus is on how to efficiently provide computing performance in situations where the capabilities of a standard microprocessor do not suffice, or its energy requirements would be excessive.

As an alternative, we propose adaptive computers: combining a smaller, low-power microprocessor with a highly optimized reconfigurable compute unit. The structure of the latter can then be optimally adapted to the precise needs of the current application, and thus provide the required compute power with reduced energy consumption.

To achieve this goal, we realize hardware demonstrators for such computer architectures (including the required operating system ports), and evaluate these using practical applications from a variety of fields. After very promising results, we have now concentrated on making the potential of such computers available even to developers who lack the skills in hardware design that are still required to program such systems. To this end, we have been working on a complete compile flow for partitioning a program in a software high-level programming language for separate execution on the two compute units. The part assigned to the reconfigurable compute unit is then processed further using techniques from hardware synthesis and physical chip design (mapping, placement, routing).

Many of our research efforts rely on support by motivated students with appropriate skills and experience. Thus, our group also develops lectures and labs on the wide range of topics listed above.


  • Presentation at H2RC 2019

    At the Heterogeneous High-performance Reconfigurable Computing workshop (H2RC 2019), Lukas Sommer presented our paper High-Throughput Multi-Threaded Sum-Product Network Inference in the Reconfigurable Cloud, authored by Micha Ober, Jaco Hofmann, Lukas Sommer, Lukas Weber and Andreas Koch.

    In this work, we presented an extension of our TaPaSCo open-source framework to F1 instances available in Amazon’s AWS EC2 cloud. To demonstrate the potential of this platform, we ported our Sum-Product Accelerator to the reconfigurable cloud.

    Users interested in using TaPaSCo for AWS EC2 F1 instances can track the status of the integration into mainline TaPaSCo in the TaPaSCo wiki.

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    By Lukas Sommer, 17.11.2019

  • Julian Oppermann defends his Ph.D.-thesis

    On October 30th, 2019 Julian Oppermann successfully defended his Ph.D.-thesis Advances in ILP-based Modulo Scheduling for High-Level Synthesis. In his work, Julian was able to significantly advance the state-of-the-art in modulo scheduling for High-Level Synthesis.

    Congratulations to Dr.-Ing. Julian Oppermann!

    By Lukas Sommer, 30.10.2019

  • Leonardo Solis-Vasquez defends his Ph.D.-thesis

    On October 14th, 2019 Leonardo Solis-Vasquez successfully defended his Ph.D.-thesis entitled Accelerating Molecular Docking by Parallelized Heterogeneous Computing - a Case Study of Performance, Quality of Results, and Energy-Efficiency using CPUs, GPUs and FPGAs. In his work, Leonardo contributed accelerated implementations for GPUs and FPGAs to AutoDock, a framework for molecular docking in drug design.

    Congratulations to Dr.-Ing. Leonardo Solis-Vasquez!

    By Lukas Sommer, 14.10.2019

  • Two papers accepted for FPT 2019

    Two submissions by ESA have been accepted for publication at FPT 2019.

    The first paper by Julian Oppermann, Lukas Sommer, Lukas Weber, Melanie Reuter-Oppermann, Andreas Koch and Oliver Sinnen is titled SkyCastle: A Resource-Aware Multi-Loop Scheduler for High-Level Synthesis. In this paper, we developed a resource-aware approach to modulo-scheduling, that integrates allocation and scheduling into a single formulation. This allows to optimize performance by pipelining multiple loops in a kernel while maintaining a given resource allocation.

    The second paper by Lukas Weber, Lukas Sommer, Julian Oppermann, Alejandro Molina, Kristian Kersting and Andreas Koch is titled Resource-Efficient Logarithmic Number Scale Arithmetic for SPN Inference on FPGAs. As part of this work, we developed hardware arithmetic operators using the so-called Logarithmic Number System (LNS) for Sum-Product Network inference on FPGAs. In this use-case, the use of LNS allows to save a significant amount of hardware resources while maintaining sufficient accuracy.

    By Lukas Sommer, 8.10.2019

  • Paper accepted for ReConFig 2019

    The paper titled A Catalog and In-Hardware Evaluation of Open-Source Drop-In Compatible RISC-V Softcore Processors by Carsten Heinz, Yannick Lavan, Jaco Hofmann and Andreas Koch has been accepted for presentation at ReConFig 2019.

    Carsten and his team developed a catalog of open-source RISC-V cores for use with our TaPaSCo framework and conducted an extensive evaluation of these cores on different platforms.

    The catalog of RISC-V cores and the wrappers for TaPaSCo are publicly available on Github.

    By Lukas Sommer, 30.09.2019

  • Open PhD Positions

    The Embedded Systems and Applications group is actively looking to fill a number of PhD positions in the area of hardware/software-systems.

    If you are interested, please feel free to contact us.

    By Prof. Dr-Ing. Andreas Koch, 15.07.2019

You can find more news in our archive.