Staff photo for

Forschungsgebiete

Andreas Koch befasst sich schwerpunktmäßig mit adaptiven Rechensystemen. Es handelt sich dabei um Computer, bei denen auch die Hardware in Teilaspekten dynamisch an die Erfordernisse der gerade ablaufenden Software angepasst werden kann. Die Palette der einzelnen Arbeitsgebiete reicht dabei von der Entwicklung geeigneter CAD-Werkzeuge (spezialisierte Compiler und Chip-Layoutwerkzeuge) über die Konzeption von Rechnerarchitekturen bis hin zum praktischen Aufbau und der Erprobung von Prototypensystemen. Daneben ist Herr Koch auch an objektorientierten Programmiersprachen und Software-Engineering interessiert.

Lebenslauf

  • 2005

    Habilitation und Ruf an die TU Darmstadt

  • 1999

    Post-Doktorand (TU Braunschweig, EIS)

  • 1997-1999

    Post-Doktorand (UC Berkeley, Arbeitsgruppe BRASS)

  • 1997

    Promotion zum Dr.-Ing. (TU Braunschweig, EIS)

  • 1992

    Diplom in Informatik (TU Braunschweig)

Publications

  1. Hofmann, J., Thostrup, L., Ziegler, T., Binnig, C., and Koch, A. (2019). High-Performance In-Network Data Processing. In International Workshop on Accelerating Analytics and Data Management Systems Using Modern Processor and Storage Architectures, ADMS@VLDB 2019, Los Angeles, United States.
    Bibtex
    @inproceedings{adms2019,
      author = {Hofmann, Jaco and Thostrup, Lasse and Ziegler, Tobias and Binnig, Carsten and Koch, Andreas},
      title = {High-Performance In-Network Data Processing},
      booktitle = {International Workshop on Accelerating Analytics and Data Management
                     Systems Using Modern Processor and Storage Architectures, ADMS@VLDB
                     2019, Los Angeles, United States.},
      year = {2019}
    }
    
  2. Sommer, L., Stock, F., Solis-Vasquez, L., and Koch, A. (2019). WIP: Automotive Benchmark Suite for Parallel Programming Models on Embedded Heterogeneous Platforms. In Proceedings of the International Conference on Embedded Software (accepted for publication 07/2019), EMSOFT ’19. Piscataway, NJ, USA: IEEE Press.
    Bibtex
    @inproceedings{emsoft2019,
      author = {Sommer, Lukas and Stock, Florian and Solis-Vasquez, Leonardo and Koch, Andreas},
      title = {WIP: Automotive Benchmark Suite for Parallel Programming Models on Embedded Heterogeneous Platforms},
      booktitle = {Proceedings of the International Conference on Embedded Software (accepted for publication 07/2019)},
      series = {EMSOFT '19},
      year = {2019},
      location = {New York, NY, USA},
      publisher = {IEEE Press},
      address = {Piscataway, NJ, USA}
    }
    
  3. Sommer, L., Stock, F., Solis-Vasquez, L., and Koch, A. (2019). EPHoS: Evaluation of Programming - Models for Heterogeneous Systems. FAT-Schriftenreihe 317. Forschungsvereinigung Automobiltechik.
    Preprint
    Bibtex
    @article{fat317,
      title = {EPHoS: Evaluation of Programming - Models for Heterogeneous Systems},
      author = {Sommer, Lukas and Stock, Florian and Solis-Vasquez, Leonardo and Koch, Andreas},
      booktitle = {FAT-Schriftenreihe 317},
      year = {2019},
      publisher = {Forschungsvereinigung Automobiltechik},
      preprint = {https://www.vda.de/de/services/Publikationen/fat-schriftenreihe-317.html}
    }
    
  4. Wolf, D., Ruschke, T., Hochberger, C., Engel, A., and Koch, A. (2019). UltraSynth: Integration of a CGRA into a Control Engineering Environment. In C. Hochberger, B. Nelson, A. Koch, R. Woods, and P. Diniz (Eds.), Applied Reconfigurable Computing (pp. 247–261). Cham: Springer International Publishing.
    Preprint
    Bibtex
    @inproceedings{engel2019ultrasynth,
      author = {Wolf, Dennis and Ruschke, Tajas and Hochberger, Christian and Engel, Andreas and Koch, Andreas},
      editor = {Hochberger, Christian and Nelson, Brent and Koch, Andreas and Woods, Roger and Diniz, Pedro},
      title = {UltraSynth: Integration of a CGRA into a Control Engineering Environment},
      booktitle = {Applied Reconfigurable Computing},
      year = {2019},
      publisher = {Springer International Publishing},
      address = {Cham},
      pages = {247--261},
      isbn = {978-3-030-17227-5},
      preprint = {https://link.springer.com/chapter/10.1007/978-3-030-17227-5_18}
    }
    
  5. Korinth, J., Hofmann, J., Heinz, C., and Koch, A. (2019). The TaPaSCo Open-Source Toolflow for the Automated Composition of Task-Based Parallel Reconfigurable Computing Systems. In International Symposium on Applied Reconfigurable Computing (ARC).
    Preprint
    Bibtex
    @inproceedings{korinth2019ttpscostactbprcs,
      title = {The TaPaSCo Open-Source Toolflow for the Automated Composition of Task-Based Parallel Reconfigurable Computing Systems},
      author = {Korinth, Jens and Hofmann, Jaco and Heinz, Carsten and Koch, Andreas},
      booktitle = {International Symposium on Applied Reconfigurable Computing (ARC)},
      year = {2019}
    }
    
  6. Oppermann, J., Sittel, P., Kumm, M., Reuter-Oppermann, M., Koch, A., and Sinnen, O. (2019). Design-Space Exploration with Multi-Objective Resource-Aware Modulo Scheduling. In International European Conference on Parallel and Distributed Computing (Euro-Par), Göttingen, Germany.
    Preprint
    Bibtex
    @inproceedings{oppermann2019dsemorams,
      author = {Oppermann, Julian and Sittel, Patrick and Kumm, Martin and Reuter{-}Oppermann, Melanie and Koch, Andreas and Sinnen, Oliver},
      title = {{Design-Space Exploration with Multi-Objective Resource-Aware Modulo Scheduling}},
      booktitle = {International European Conference on Parallel and Distributed Computing (Euro-Par), Göttingen, Germany},
      year = {2019}
    }
    
  7. Oppermann, J., Reuter-Oppermann, M., Sommer, L., Koch, A., and Sinnen, O. (2019). Exact and Practical Modulo Scheduling for High-Level Synthesis. TRETS, 12(2), 8:1–8:26. doi: 10.1145/3317670
    Preprint
    Bibtex
    @article{oppermann2019epmshs,
      author = {Oppermann, Julian and Reuter{-}Oppermann, Melanie and Sommer, Lukas and Koch, Andreas and Sinnen, Oliver},
      title = {Exact and Practical Modulo Scheduling for High-Level Synthesis},
      journal = {{TRETS}},
      volume = {12},
      number = {2},
      pages = {8:1--8:26},
      year = {2019},
      doi = {10.1145/3317670}
    }
    
  8. Kruppe, R., Oppermann, J., Sommer, L., and Koch, A. (2019). Extending LLVM for Lightweight SPMD Vectorization: Using SIMD and Vector Instructions Easily from Any Language . In 2019 International Symposium on Code Generation and Optimization.
    Preprint
    Bibtex
    @inproceedings{kruppe2019ellvmlspmdvusimdvieal,
      title = {Extending LLVM for Lightweight SPMD Vectorization: Using SIMD and Vector Instructions Easily from Any Language },
      author = {Kruppe, Robin and Oppermann, Julian and Sommer, Lukas and Koch, Andreas},
      booktitle = {2019 International Symposium on Code Generation and Optimization},
      year = {2019}
    }
    
  9. Sommer, L., Oppermann, J., Molina, A., Binnig, C., Kersting, K., and Koch, A. (2018). Automatic Mapping of the Sum-Product Network Inference Problem to FPGA-based Accelerators. In IEEE International Conference on Computer Design (ICCD).
    Preprint
    Bibtex
    @inproceedings{sommer2018amspnipfpgaa,
      title = {Automatic Mapping of the Sum-Product Network Inference Problem to FPGA-based Accelerators},
      author = {Sommer, Lukas and Oppermann, Julian and Molina, Alejandro and Binnig, Carsten and Kersting, Kristian and Koch, Andreas},
      booktitle = {IEEE International Conference on Computer Design (ICCD)},
      year = {2018},
      organizazion = {IEEE}
    }
    
  10. Solis-Vasquez, L., and Koch, A. (2018). A Case Study in Using OpenCL on FPGAs: Creating an Open-Source Accelerator of the AutoDock Molecular Docking Software . In Fifth International Workshop on FPGAs for Software Programmers (FSP).
    Preprint Material
    Bibtex
    @inproceedings{solis-vasquez2018acsuoclfpgacosaadmds,
      title = {A Case Study in Using OpenCL on FPGAs: Creating an Open-Source Accelerator of the AutoDock Molecular Docking Software },
      author = {Solis-Vasquez, Leonardo and Koch, Andreas},
      booktitle = {Fifth International Workshop on FPGAs for Software Programmers (FSP)},
      year = {2018},
      material = {https://git.esa.informatik.tu-darmstadt.de/docking/ocladock-fpga}
    }
    
  11. Oppermann, J., Vollbrecht, S., Reuter-Oppermann, M., Sinnen, O., and Koch, A. (2018). Work in Progress: GeMS: A Generator for Modulo Scheduling Problems. In Intl. Conf. on Compilers, Architectures and Synthesis For Embedded Systems (CASES).
    Preprint
    Bibtex
    @inproceedings{oppermann2018wpgmsagmsp,
      title = {Work in Progress: GeMS: A Generator for Modulo Scheduling Problems},
      author = {Oppermann, Julian and Vollbrecht, Sebastian and Reuter-Oppermann, Melanie and Sinnen, Oliver and Koch, Andreas},
      booktitle = {Intl. Conf. on Compilers,  Architectures and Synthesis For Embedded Systems (CASES)},
      year = {2018}
    }
    
  12. Oppermann, J., Reuter-Oppermann, M., Sommer, L., Sinnen, O., and Koch, A. (2018). Dependence Graph Preprocessing for Faster Exact Modulo Scheduling in High-level Synthesis. In Intl. Conf. on Field Programmable Logic and Applications (FPL).
    Preprint
    Bibtex
    @inproceedings{oppermann2018dgpfemshs,
      title = {Dependence Graph Preprocessing for Faster Exact Modulo Scheduling in High-level Synthesis},
      author = {Oppermann, Julian and Reuter-Oppermann, Melanie and Sommer, Lukas and Sinnen, Oliver and Koch, Andreas},
      booktitle = {Intl. Conf. on Field Programmable Logic and Applications (FPL)},
      year = {2018}
    }
    
  13. Sittel, P., Kumm, M., Oppermann, J., Möller, K., Zipf, P., and Koch, A. (2018). ILP-based Modulo Scheduling and Binding for Register Minimization. In Intl. Conf. on Field Programmable Logic and Applications (FPL).
    Preprint
    Bibtex
    @inproceedings{sittel2018ilpmsbrm,
      title = {ILP-based Modulo Scheduling and Binding for Register Minimization},
      author = {Sittel, Patrick and Kumm, Martin and Oppermann, Julian and Möller, Konrad and Zipf, Peter and Koch, Andreas},
      booktitle = {Intl. Conf. on Field Programmable Logic and Applications (FPL)},
      year = {2018}
    }
    
  14. Sittel, P., Oppermann, J., Kumm, M., Koch, A., and Zipf, P. (2018). HatScheT: A Contribution to Agile HLS. In FPGAs for Software Programmers (FSP).
    Preprint
    Bibtex
    @inproceedings{sittel2018hstacahls,
      title = {HatScheT: A Contribution to Agile HLS},
      author = {Sittel, Patrick and Oppermann, Julian and Kumm, Martin and Koch, Andreas and Zipf, Peter},
      booktitle = {FPGAs for Software Programmers (FSP)},
      year = {2018}
    }
    
  15. Sommer, L., Oppermann, J., Molina, A., Binnig, C., Kersting, K., and Koch, A. (2018). Automatic Synthesis of FPGA-based Accelerators for the Sum-Product Network Inference Problem. In ICML 2018 Workshop on Tractable Probabilistic Models (TPM).
    Preprint
    Bibtex
    @inproceedings{sommer2018asfpgaaspnip,
      title = {Automatic Synthesis of FPGA-based Accelerators for the Sum-Product Network Inference Problem},
      author = {Sommer, Lukas and Oppermann, Julian and Molina, Alejandro and Binnig, Carsten and Kersting, Kristian and Koch, Andreas},
      booktitle = {ICML 2018 Workshop on Tractable Probabilistic Models (TPM)},
      year = {2018},
      organizazion = {ICML}
    }
    
  16. Kruppe, R., Oppermann, J., and Koch, A. (2018). Supporting the RISC-V Vector Extensions in LLVM. In 2018 European LLVM Developers Meeting.
    Slides Video Material
    Bibtex
    @inproceedings{kruppe2018sriscvvellvm,
      title = {Supporting the RISC-V Vector Extensions in LLVM},
      author = {Kruppe, Robin and Oppermann, Julian and Koch, Andreas},
      booktitle = {2018 European LLVM Developers Meeting},
      year = {2018},
      video = {https:/youtu.be/iSMLYHRlNVc},
      slides = {http://llvm.org/devmtg/2018-04/slides/Kruppe-Supporting%20the%20Risc-V%20vector%20ext.pdf},
      material = {https://llvm.org/devmtg/2018-04/talks.html#Lightning_18}
    }
    
  17. Sommer, L., Oppermann, J., Korinth, J., and Koch, A. (2018). Offloading OpenMP Target Regions to FPGA Accelerators Using LLVM. In 2018 European LLVM Developers Meeting.
    Preprint
    Bibtex
    @inproceedings{sommer2018oomptrfpgaaullvm,
      title = {Offloading OpenMP Target Regions to FPGA Accelerators Using LLVM},
      author = {Sommer, Lukas and Oppermann, Julian and Korinth, Jens and Koch, Andreas},
      booktitle = {2018 European LLVM Developers Meeting},
      year = {2018}
    }
    
  18. Vincon, T., Haddock, S., Riegger, C., Oppermann, J., Koch, A., and Petrov, I. (2018). NoFTL-KV: Tackling Write-Amplification on KV-Stores with Native Storage Management. In Proc. of the 21st International Conference on Extending Database Technology (EDBT).
    Preprint
    Bibtex
    @inproceedings{vincon2018nftlkvtwakvsnsm,
      title = {NoFTL-KV: Tackling Write-Amplification on KV-Stores with Native Storage Management},
      author = {Vincon, Tobias and Haddock, Sergey and Riegger, Christian and Oppermann, Julian and Koch, Andreas and Petrov, Ilia},
      booktitle = {Proc. of the 21st International Conference on Extending Database Technology (EDBT)},
      year = {2018}
    }
    
  19. Liebig, B., Oppermann, J., Sinnen, O., and Koch, A. (2018). Improved High-Level Synthesis for Complex CellML Models. In Proc. 14th International Symposium on Applied Reconfigurable Computing (ARC).
    Preprint
    Bibtex
    @inproceedings{liebig2018ihlsccmlm,
      title = {Improved High-Level Synthesis for Complex CellML Models},
      author = {Liebig, Björn and Oppermann, Julian and Sinnen, Oliver and Koch, Andreas},
      booktitle = {Proc. 14th International Symposium on Applied Reconfigurable Computing (ARC)},
      year = {2018}
    }
    
  20. Engel, A., and Koch, A. (2017). Energy-Efficient Reconfiguration of Flash-based FPGAs in Heterogeneous Wireless Sensor Nodes. In IEEE Proc. International Conference on ReConFigurable Computing and FPGAs (ReConFig).
    Preprint
    Bibtex
    @inproceedings{engel2017eerffpgahwsn,
      title = {Energy-Efficient Reconfiguration of Flash-based FPGAs in Heterogeneous Wireless Sensor Nodes},
      author = {Engel, Andreas and Koch, Andreas},
      booktitle = {IEEE Proc. International Conference on ReConFigurable Computing and FPGAs (ReConFig)},
      year = {2017},
      organizazion = {IEEE}
    }
    
  21. Sommer, L., Oppermann, J., Hofmann, J., and Koch, A. (2017). Synthesis of Interleaved Multithreaded Accelerators from OpenMP Loops. In 2017 International Conference on Reconfigurable Computing and FPGAs (ReConFig’17).
    Preprint
    Bibtex
    @inproceedings{sommer2017simaompl,
      title = {Synthesis of Interleaved Multithreaded Accelerators from OpenMP Loops},
      author = {Sommer, Lukas and Oppermann, Julian and Hofmann, Jaco and Koch, Andreas},
      booktitle = {2017 International Conference on Reconfigurable Computing and FPGAs (ReConFig'17)},
      year = {2017},
      organizazion = {IEEE}
    }
    
  22. Sommer, L., Korinth, J., and Koch, A. (2017). OpenMP Device Offloading to FPGA Accelerators. In International Conference on Application-specific Systems, Architectures and Processors (ASAP).
    Preprint Poster
    Bibtex
    @inproceedings{sommer2017ompdofpgaa,
      title = {OpenMP Device Offloading to FPGA Accelerators},
      author = {Sommer, Lukas and Korinth, Jens and Koch, Andreas},
      booktitle = {International Conference on Application-specific Systems, Architectures and Processors (ASAP)},
      year = {2017}
    }
    
  23. Oppermann, J., Sommer, L., and Koch, A. (2017). SpExSim: assessing kernel suitability for C-based high-level hardware synthesis. In Journal of Supercomputing.
    Preprint
    Bibtex
    @inproceedings{oppermann2017sesc,
      title = {SpExSim: assessing kernel suitability for C-based high-level hardware synthesis},
      author = {Oppermann, Julian and Sommer, Lukas and Koch, Andreas},
      booktitle = {Journal of Supercomputing},
      year = {2017},
      preprint = {http://link.springer.com/article/10.1007/s11227-017-2101-z}
    }
    
  24. Solis-Vasquez, L., and Koch, A. (2017). A Performance and Energy Evaluation of OpenCL-accelerated Molecular Docking. In Fifth International Workshop on OpenCL (IWOCL).
    Preprint Material
    Bibtex
    @inproceedings{solis-vasquez2017apeeoclmd,
      title = {A Performance and Energy Evaluation of OpenCL-accelerated Molecular Docking},
      author = {Solis-Vasquez, Leonardo and Koch, Andreas},
      booktitle = {Fifth International Workshop on OpenCL (IWOCL)},
      year = {2017},
      material = {https://git.esa.informatik.tu-darmstadt.de/docking/ocladock}
    }
    
  25. Liebig, B., and Koch, A. (2016). High-Level Synthesis of Resource-Shared Microarchitectures from Irregular Complex C-Code. In International Conference on Field-Programmable Technology (FPT).
    Preprint
    Bibtex
    @inproceedings{liebig2016hlsrsmiccc,
      title = {High-Level Synthesis of Resource-Shared Microarchitectures from Irregular Complex C-Code},
      author = {Liebig, Björn and Koch, Andreas},
      booktitle = {International Conference on Field-Programmable Technology (FPT)},
      year = {2016}
    }
    
  26. Hofmann, J., Korinth, J., and Koch, A. (2016). A Scalable Latency-Insensitive Architecture for FPGA-Accelerated Semi-Global Matching in Stereo Vision Applications. In IEEE Proc. International Conference on ReConFigurable Computing and FPGAs (ReConFig).
    Preprint
    Bibtex
    @inproceedings{hofmann2016asliafpgaasgmsva,
      title = {A Scalable Latency-Insensitive Architecture for FPGA-Accelerated Semi-Global Matching in Stereo Vision Applications},
      author = {Hofmann, Jaco and Korinth, Jens and Koch, Andreas},
      booktitle = {IEEE Proc. International Conference on ReConFigurable Computing and FPGAs (ReConFig)},
      year = {2016},
      organizazion = {IEEE}
    }
    
  27. Engel, A., and Koch, A. (2016). Heterogeneous Wireless Sensor Nodes That Target the Internet of Things. In IEEE Micro Magazine.
    Preprint
    Bibtex
    @inproceedings{engel2016hwsnttit,
      title = {Heterogeneous Wireless Sensor Nodes That Target the Internet of Things},
      author = {Engel, Andreas and Koch, Andreas},
      booktitle = {IEEE Micro Magazine},
      year = {2016},
      organizazion = {IEEE}
    }
    
  28. Sommer, L., Oppermann, J., and Koch, A. (2016). C-based Synthesis of Area-Efficient Accelerators for OpenMP Worksharing Loops. In Second International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC).
    Preprint
    Bibtex
    @inproceedings{sommer2016csaeaompwl,
      title = {C-based Synthesis of Area-Efficient Accelerators for OpenMP Worksharing Loops},
      author = {Sommer, Lukas and Oppermann, Julian and Koch, Andreas},
      booktitle = {Second International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)},
      year = {2016}
    }
    
  29. Oppermann, J., Koch, A., Reuter-Oppermann, M., and Sinnen, O. (2016). ILP-based Modulo Scheduling for High-level Synthesis. In International Conference on Compilers, Architectures and Synthesis For Embedded Systems (CASES).
    Preprint Material
    Bibtex
    @inproceedings{oppermann2016ilpmshs,
      title = {ILP-based Modulo Scheduling for High-level Synthesis},
      author = {Oppermann, Julian and Koch, Andreas and Reuter-Oppermann, Melanie and Sinnen, Oliver},
      booktitle = {International Conference on Compilers, Architectures and Synthesis For Embedded Systems (CASES)},
      year = {2016},
      material = {http://dx.doi.org/10.1145/2968455.2968512}
    }
    
  30. Brugnoni, S., Corbat, T., Sommerlad, P., Suter, T., Korinth, J., Chevallerie, D. de la, and Koch, A. (2016). Automated Generation of Reconfigurable Systems-on-Chip by Interactive Code Transformations for High-Level Synthesis. In Third International Workshop on FPGAs Software Programmers (FSP).
    Preprint
    Bibtex
    @inproceedings{brugnoni2016agrscicthls,
      title = {Automated Generation of Reconfigurable Systems-on-Chip by Interactive Code Transformations for High-Level Synthesis},
      author = {Brugnoni, Silvano and Corbat, Thomas and Sommerlad, Peter and Suter, Toni and Korinth, Jens and de la Chevallerie, David and Koch, Andreas},
      booktitle = {Third International Workshop on FPGAs Software Programmers (FSP)},
      year = {2016}
    }
    
  31. Hochberger, C., Koch, A., and Weinhardt, M. (2016). Third International Workshop on FPGAs for Software Programmers (FSP 2016). In Proceedings Volume.
    Bibtex
    @inproceedings{hochberger2016tiwfpgaspfsp,
      title = {Third International Workshop on FPGAs for Software Programmers (FSP 2016)},
      author = {Hochberger, Christian and Koch, Andreas and Weinhardt, Markus},
      booktitle = {Proceedings Volume},
      year = {2016}
    }
    
  32. Oppermann, J., and Koch, A. (2016). Detecting Kernels Suitable for C-based High-Level Hardware Synthesis. In 2nd International Workshop on Reengineering for Parallelism in Heterogeneous Parallel Platforms (RePara).
    Preprint
    Bibtex
    @inproceedings{oppermann2016dkschlhs,
      title = {Detecting Kernels Suitable for C-based High-Level Hardware Synthesis},
      author = {Oppermann, Julian and Koch, Andreas},
      booktitle = {2nd International Workshop on Reengineering for Parallelism in Heterogeneous Parallel Platforms (RePara)},
      year = {2016}
    }
    
  33. Hofmann, J., Korinth, J., and Koch, A. (2016). A Scalable High-Performance Hardware Architecture for Real-Time Stereo Vision by Semi-Global Matching. In IEEE Conference on Computer Vision and Pattern Recognition (CVPR) Workshops.
    Preprint
    Bibtex
    @inproceedings{hofmann2016ashphartsvsgm,
      title = {A Scalable High-Performance Hardware Architecture for Real-Time Stereo Vision by Semi-Global Matching},
      author = {Hofmann, Jaco and Korinth, Jens and Koch, Andreas},
      booktitle = {IEEE Conference on Computer Vision and Pattern Recognition (CVPR) Workshops},
      year = {2016},
      organizazion = {IEEE}
    }
    
  34. Huthmann, J., and Koch, A. (2015). Optimized High-Level Synthesis of SMT Multi-Threaded Hardware Accelerators. In International Conference on Field-Programmable Technology (FPT).
    Preprint
    Bibtex
    @inproceedings{huthmann2015ohlssmtmtha,
      title = {Optimized High-Level Synthesis of SMT Multi-Threaded Hardware Accelerators},
      author = {Huthmann, Jens and Koch, Andreas},
      booktitle = {International Conference on Field-Programmable Technology (FPT)},
      year = {2015}
    }
    
  35. Korinth, J., Chevallerie, D. de la, and Koch, A. (2015). ThreadPoolComposer – An Open-Source FPGA Toolchain for Software Developers. In Second International Workshop on FPGAs Software Programmers (FSP).
    Preprint
    Bibtex
    @inproceedings{korinth2015tpcaosfpgatsd,
      title = {ThreadPoolComposer – An Open-Source FPGA Toolchain for Software Developers},
      author = {Korinth, Jens and de la Chevallerie, David and Koch, Andreas},
      booktitle = {Second International Workshop on FPGAs Software Programmers (FSP)},
      year = {2015}
    }
    
  36. Korinth, J., Chevallerie, D. de la, and Koch, A. (2015). An Open-Source Tool Flow for the Composition of Reconfigurable Hardware Thread Pool Architectures. In The 23rd IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM).
    Preprint
    Bibtex
    @inproceedings{korinth2015aostfcrhtpa,
      title = {An Open-Source Tool Flow for the Composition of Reconfigurable Hardware Thread Pool Architectures},
      author = {Korinth, Jens and de la Chevallerie, David and Koch, Andreas},
      booktitle = {The 23rd IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM)},
      year = {2015},
      organizazion = {IEEE}
    }
    
  37. Chevallerie, D. de la, Korinth, J., and Koch, A. (2015). ffLink: A Lightweight High-Performance Open-Source PCI Express Gen3 Interface for Reconfigurable Accelerators. In ACM SIGARCH Computer Architecture News.
    Preprint
    Bibtex
    @inproceedings{de2015lalhpospciegira,
      title = {ffLink: A Lightweight High-Performance Open-Source PCI Express Gen3 Interface for Reconfigurable Accelerators},
      author = {de la Chevallerie, David and Korinth, Jens and Koch, Andreas},
      booktitle = {ACM SIGARCH Computer Architecture News},
      year = {2015},
      organizazion = {ACM}
    }
    
  38. Engel, A., and Koch, A. (2015). Accelerated Clock Drift Estimation for High-Precision Wireless Time-Synchronization. In IEEE Proc. Conference on Local Computer Networks (LCN).
    Preprint
    Bibtex
    @inproceedings{engel2015acdehpwts,
      title = {Accelerated Clock Drift Estimation for High-Precision Wireless Time-Synchronization},
      author = {Engel, Andreas and Koch, Andreas},
      booktitle = {IEEE Proc. Conference on Local Computer Networks (LCN)},
      year = {2015},
      organizazion = {IEEE}
    }
    
  39. Engel, A., and Koch, A. (2015). DEMO: The Need for Wireless Clock Drift Estimation and Its Acceleration on a Heterogeneous Sensor Node. In IEEE Proc. Conference on Local Computer Networks (LCN).
    Preprint
    Bibtex
    @inproceedings{engel2015demotnwcdeiahsn,
      title = {DEMO: The Need for Wireless Clock Drift Estimation and Its Acceleration on a Heterogeneous Sensor Node},
      author = {Engel, Andreas and Koch, Andreas},
      booktitle = {IEEE Proc. Conference on Local Computer Networks (LCN)},
      year = {2015},
      organizazion = {IEEE}
    }
    
  40. Engel, A., Siebel, T., and Koch, A. (2015). A Heterogeneous System Architecture for Low-Power Wireless Sensor Nodes in Compute-intensive Distributed Applications. In IEEE Proc. Conference on Local Computer Networks (LCN).
    Preprint
    Bibtex
    @inproceedings{engel2015ahsalpwsncda,
      title = {A Heterogeneous System Architecture for Low-Power Wireless Sensor Nodes in Compute-intensive Distributed Applications},
      author = {Engel, Andreas and Siebel, Thomas and Koch, Andreas},
      booktitle = {IEEE Proc. Conference on Local Computer Networks (LCN)},
      year = {2015},
      organizazion = {IEEE}
    }
    
  41. Oppermann, J., Koch, A., Yu, T., and Sinnen, O. (2015). Domain-specific Optimisation for the High-level Synthesis of CellML-based Simulation Accelerators. In IEEE Proc. Intl. Conf. on Field Programmable Logic and Applications (FPL).
    Preprint
    Bibtex
    @inproceedings{oppermann2015dohscmlsa,
      title = {Domain-specific Optimisation for the High-level Synthesis of CellML-based Simulation Accelerators},
      author = {Oppermann, Julian and Koch, Andreas and Yu, Ting and Sinnen, Oliver},
      booktitle = {IEEE Proc.  Intl. Conf. on Field Programmable Logic and Applications (FPL)},
      year = {2015},
      organizazion = {IEEE}
    }
    
  42. Engel, A., Hildebrand, P., Pott, P., Schlaak, F., and Koch, A. (2014). Hardware-Accelerated Embedded Controller for a Piezo-electric Haptic Feedback System. In Proc. 14th International Conference on New Actuators and Drive Systems.
    Preprint
    Bibtex
    @inproceedings{engel2014haecphfs,
      title = {Hardware-Accelerated Embedded Controller for a Piezo-electric Haptic Feedback System},
      author = {Engel, Andreas and Hildebrand, Paul and Pott, P. and Schlaak, F. and Koch, Andreas},
      booktitle = {Proc. 14th International Conference on New Actuators and Drive Systems},
      year = {2014}
    }
    
  43. Engel, A., and Koch, A. (2014). Hardware-Accelerated Data Compression in Low-Power Wireless Sensor Networks. In LNCS Proc. 10th International Symposium on Applied Reconfigurable Computing (ARC).
    Preprint
    Bibtex
    @inproceedings{engel2014hadclpwsn,
      title = {Hardware-Accelerated Data Compression in Low-Power Wireless Sensor Networks},
      author = {Engel, Andreas and Koch, Andreas},
      booktitle = {LNCS Proc. 10th International Symposium on Applied Reconfigurable Computing (ARC)},
      year = {2014},
      organizazion = {LNCS}
    }
    
  44. Hochberger, C., Jung, J., Engel, A., and Koch, A. (2014). Synthilation: JIT-Compilation of Microinstruction Sequences in AMIDAR Processors. In IEEE Proc. Conference on Design & Architectures for Signal & Image Processing (DASIP).
    Preprint
    Bibtex
    @inproceedings{hochberger2014sjitcmsamidarp,
      title = {Synthilation: JIT-Compilation of Microinstruction Sequences in AMIDAR Processors},
      author = {Hochberger, Christian and Jung, Johannes and Engel, Andreas and Koch, Andreas},
      booktitle = {IEEE Proc. Conference on Design & Architectures for Signal & Image Processing (DASIP)},
      year = {2014},
      organizazion = {IEEE}
    }
    
  45. Wink, T., and Koch, A. (2014). PHAT: A TECHNOLOGY FOR PROTOTYPING PARALLEL HETEROGENEOUS ARCHITECTURES. In IEEE Proc. Conference on Design & Architectures for Signal & Image Processing (DASIP).
    Preprint
    Bibtex
    @inproceedings{wink2014phatatechnologyforprototypingparallelheterogeneousarchitectures,
      title = {PHAT: A TECHNOLOGY FOR PROTOTYPING PARALLEL HETEROGENEOUS ARCHITECTURES},
      author = {Wink, Thorsten and Koch, Andreas},
      booktitle = {IEEE Proc. Conference on Design & Architectures for Signal & Image Processing (DASIP)},
      year = {2014},
      organizazion = {IEEE}
    }
    
  46. Huthmann, J., Oppermann, J., and Koch, A. (2014). Automatic high-level synthesis of multi-threaded hardware accelerators. In IEEE Proc. Intl. Conf. on Field Programmable Logic and Applications (FPL).
    Preprint
    Bibtex
    @inproceedings{huthmann2014a,
      title = {Automatic high-level synthesis of multi-threaded hardware accelerators},
      author = {Huthmann, Jens and Oppermann, Julian and Koch, Andreas},
      booktitle = {IEEE Proc.  Intl. Conf. on Field Programmable Logic and Applications (FPL)},
      year = {2014},
      organizazion = {IEEE}
    }
    
  47. Liebig, B., and Koch, A. (2014). Low-Latency Double-Precision Floating-Point Division for FPGAs. In IEEE Proc. Intl. Conf. on Field-Programmable Technology (FPT).
    Preprint
    Bibtex
    @inproceedings{liebig2014lldpfpdfpga,
      title = {Low-Latency Double-Precision Floating-Point Division for FPGAs},
      author = {Liebig, Björn and Koch, Andreas},
      booktitle = {IEEE Proc. Intl. Conf. on Field-Programmable Technology (FPT)},
      year = {2014},
      organizazion = {IEEE}
    }
    
  48. Chevallerie, D. de la, Korinth, J., and Koch, A. (2014). Integrating FPGA-based Processing Elements into a Runtime for Parallel Heterogeneous Computing. In IEEE Proc. Intl. Conf. on Field-Programmable Technology (FPT).
    Preprint
    Bibtex
    @inproceedings{de2014ifpgaperphc,
      title = {Integrating FPGA-based Processing Elements into a Runtime for Parallel Heterogeneous Computing},
      author = {de la Chevallerie, David and Korinth, Jens and Koch, Andreas},
      booktitle = {IEEE Proc. Intl. Conf. on Field-Programmable Technology (FPT)},
      year = {2014},
      organizazion = {IEEE}
    }
    
  49. Engel, A., Friedmann, A., Koch, M., Rohlfing, J., Siebel, T., Mayer, D., and Koch, A. (2014). Hardware-Accelerated Wireless Sensor Network for Distributed Structural Health Monitoring. In Elsevier Procedia Technology (pp. 738–747).
    Preprint
    Bibtex
    @inproceedings{engel2014hawsndshm,
      title = {Hardware-Accelerated Wireless Sensor Network for Distributed Structural Health Monitoring},
      author = {Engel, Andreas and Friedmann, Andreas and Koch, Michael and Rohlfing, Jens and Siebel, Thomas and Mayer, Dirk and Koch, Andreas},
      booktitle = {Elsevier Procedia Technology},
      pages = {738--747},
      year = {2014}
    }
    
  50. Engel, A., and Koch, A. (2014). An Energy-Efficient Wireless Routing Protocol for Distributed Structural Health Monitoring. In IEEE Proc. 7th IFIP Wireless and Mobile Networking Conference.
    Preprint
    Bibtex
    @inproceedings{engel2014aeewrpdshm,
      title = {An Energy-Efficient Wireless Routing Protocol for Distributed Structural Health Monitoring},
      author = {Engel, Andreas and Koch, Andreas},
      booktitle = {IEEE Proc. 7th IFIP Wireless and Mobile Networking Conference},
      year = {2014},
      organizazion = {IEEE}
    }
    
  51. Mühlbach, S., and Koch, A. (2014). A Reconfigurable Platform and Programming Tools for High-Level Network Applications Demonstrated as a Hardware Honeypot. In IEEE Journal on Selected Areas in Communications (pp. 1919–1932).
    Preprint
    Bibtex
    @inproceedings{muehlbach2014arppthlnadhh,
      title = {A Reconfigurable Platform and Programming Tools for High-Level Network Applications Demonstrated as a Hardware Honeypot},
      author = {Mühlbach, Sascha and Koch, Andreas},
      booktitle = {IEEE Journal on Selected Areas in Communications},
      pages = {1919--1932},
      year = {2014},
      organizazion = {IEEE}
    }
    
  52. Stock, F., Hildenbrand, D., and Koch, A. (2013). FPGA-accelerated color edge detection using a Geometric-Algebra-to-Verilog compiler. In International Symposium on System on Chip (SoC) 2013.
    Preprint
    Bibtex
    @inproceedings{stock2013fpga,
      title = {FPGA-accelerated color edge detection using a Geometric-Algebra-to-Verilog compiler},
      author = {Stock, Florian and Hildenbrand, D. and Koch, Andreas},
      booktitle = {International Symposium on System on Chip (SoC) 2013},
      year = {2013}
    }
    
  53. Liebig, B., Huthmann, J., and Koch, A. (2013). Architecture Exploration of High-Performance Floating-Point Fused Multiply-Add. In Reconfigurable Architectures Workshop.
    Preprint
    Bibtex
    @inproceedings{liebig2013aehp,
      title = {Architecture Exploration of High-Performance Floating-Point Fused Multiply-Add},
      author = {Liebig, Björn and Huthmann, Jens and Koch, Andreas},
      booktitle = {Reconfigurable Architectures Workshop},
      year = {2013}
    }
    
  54. Huthmann, J., Liebig, B., Oppermann, J., and Koch, A. (2013). Hardware/software co-compilation with the Nymble system. In Proc. of the Intl. Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC).
    Preprint
    Bibtex
    @inproceedings{huthmann2013hscc,
      title = {Hardware/software co-compilation with the Nymble system},
      author = {Huthmann, Jens and Liebig, Björn and Oppermann, Julian and Koch, Andreas},
      booktitle = {Proc. of the Intl. Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)},
      year = {2013}
    }
    
  55. Thielmann, B., Huthmann, J., and Koch, A. (2012). Memory Latency Hiding by Load Value Speculation for Reconfigurable Computers. In ACM Transactions on Reconfigurable Technology and Systems.
    Preprint
    Bibtex
    @inproceedings{thielmann2012mlhlvsrc,
      title = {Memory Latency Hiding by Load Value Speculation for Reconfigurable Computers},
      author = {Thielmann, B. and Huthmann, Jens and Koch, Andreas},
      booktitle = {ACM Transactions on Reconfigurable Technology and Systems},
      year = {2012},
      organizazion = {ACM}
    }
    
  56. Engel, A., Liebig, B., and Koch, A. (2012). Energy-efficient Heterogeneous Reconfigurable Sensor Node for Distributed Structural Health Monitoring. In IEEE Proc. Conference on Design & Architectures for Signal & Image Processing, 10-2012.
    Preprint
    Bibtex
    @inproceedings{engel2012ehrsndshm,
      title = {Energy-efficient Heterogeneous Reconfigurable Sensor Node for Distributed Structural Health Monitoring},
      author = {Engel, Andreas and Liebig, Björn and Koch, Andreas},
      booktitle = {IEEE Proc. Conference on Design & Architectures for Signal & Image Processing, 10-2012},
      year = {2012},
      organizazion = {IEEE}
    }
    
  57. Engel, A., Liebig, B., and Koch, A. (2012). HaLOEWEn: A Heterogeneous Reconfigurable Sensor Node for Distributed Structural Health Monitoring. In IEEE Proc. Conference on Design & Architectures for Signal & Image Processing, 10-2012
    .

    Preprint
    Bibtex
    @inproceedings{engel2012hloeweahrsndshm,
      title = {HaLOEWEn: A Heterogeneous Reconfigurable Sensor Node for Distributed Structural Health Monitoring},
      author = {Engel, Andreas and Liebig, Björn and Koch, Andreas},
      booktitle = {IEEE Proc. Conference on Design & Architectures for Signal & Image Processing, 10-2012
    }, year = {2012}, organizazion = {IEEE} }
  58. Muehlbach, S., and Koch, A. (2012). Malacoda: Towards High-Level Compilation of Network Security Applications on Reconfigurable Hardware. In ACM/IEEE Proc. Symposium on Architectures for Networking and Communications Systems.
    Preprint
    Bibtex
    @inproceedings{muehlbach2012mthlcnsarh,
      title = {Malacoda: Towards High-Level Compilation of Network Security Applications on Reconfigurable Hardware},
      author = {Muehlbach, S. and Koch, Andreas},
      booktitle = {ACM/IEEE Proc. Symposium on Architectures for Networking and Communications Systems},
      year = {2012},
      organizazion = {ACM/IEEE}
    }
    
  59. Thielmann, B., Huthmann, J., and Koch, A. (2012). Widening the Memory Bottleneck by Automatically-Compiled Application-Specific Speculation Mechanisms. In Embedded Systems Design with FPGAs.
    Preprint
    Bibtex
    @inproceedings{thielmann2012wmbacassm,
      title = {Widening the Memory Bottleneck by Automatically-Compiled Application-Specific Speculation Mechanisms},
      author = {Thielmann, B. and Huthmann, Jens and Koch, Andreas},
      booktitle = {Embedded Systems Design with FPGAs},
      year = {2012}
    }
    
  60. Mühlbach, S., and Koch, A. (2012). A Dynamically Reconfigured Network Platform for High-Speed Malware Collection. In International Journal of Reconfigurable Computing.
    Preprint
    Bibtex
    @inproceedings{muehlbach2012adrnphsmc,
      title = {A Dynamically Reconfigured Network Platform for High-Speed Malware Collection},
      author = {Mühlbach, Sascha and Koch, Andreas},
      booktitle = {International Journal of Reconfigurable Computing},
      year = {2012}
    }
    
  61. Mühlbach, S., and Koch, A. (2011). A Reconfigurable Hardware Platform for Secure and Efficient Malware Collection in Next-Generation High-Speed Networks. In International Journal for Information Security Research.
    Preprint
    Bibtex
    @inproceedings{muehlbach2011arhpsemcnghsn,
      title = {A Reconfigurable Hardware Platform for Secure and Efficient Malware Collection in Next-Generation High-Speed Networks},
      author = {Mühlbach, Sascha and Koch, Andreas},
      booktitle = {International Journal for Information Security Research},
      year = {2011}
    }
    
  62. Thielmann, B., Huthmann, J., Wink, T., and Koch, A. (2011). RAP: More Efficient Memory Access in Highly Speculative Execution on Reconfigurable Adaptive Computers. In IEEE Proc. International Conference on ReConFigurable Computing and FPGAs (ReConFig).
    Preprint
    Bibtex
    @inproceedings{thielmann2011rapmemahserac,
      title = {RAP: More Efficient Memory Access in Highly Speculative Execution on Reconfigurable Adaptive Computers},
      author = {Thielmann, B. and Huthmann, Jens and Wink, Thorsten and Koch, Andreas},
      booktitle = {IEEE Proc. International Conference on ReConFigurable Computing and FPGAs (ReConFig)},
      year = {2011},
      organizazion = {IEEE}
    }
    
  63. Thielmann, B., Huthmann, J., and Koch, A. (2011). PreCoRe – A Token-based Speculation Architecture For High-Level Language to Hardware Compilation. In IEEE Proc. Intl. Conf. on Field Programmable Logic and Applications (FPL).
    Preprint
    Bibtex
    @inproceedings{thielmann2011pcratsafhllhc,
      title = {PreCoRe -- A Token-based Speculation Architecture For High-Level Language to Hardware Compilation},
      author = {Thielmann, B. and Huthmann, Jens and Koch, Andreas},
      booktitle = {IEEE Proc.  Intl. Conf. on Field Programmable Logic and Applications (FPL)},
      year = {2011},
      organizazion = {IEEE}
    }
    
  64. Janda, O., Liebig, B., Lange, H., Konigorski, U., and Koch, A. (2011). Design and Hardware Implementation of a Controller for Active Damping of a Smart Structure. In Proc. 14th Intl. Adaptronic Congress.
    Preprint
    Bibtex
    @inproceedings{janda2011dhicadss,
      title = {Design and Hardware Implementation of a Controller for Active Damping of a Smart Structure},
      author = {Janda, O. and Liebig, Björn and Lange, Holger and Konigorski, U. and Koch, Andreas},
      booktitle = {Proc. 14th Intl. Adaptronic Congress},
      year = {2011}
    }
    
  65. Thielmann, B., Huthmann, J., and Koch, A. (2011). Evaluation of Speculative Execution Techniques for High-Level Language to Hardware Compilation. In IEEE Proc. 6th Intl. Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC).
    Preprint
    Bibtex
    @inproceedings{thielmann2011esethllhc,
      title = {Evaluation of Speculative Execution Techniques for High-Level Language to Hardware Compilation},
      author = {Thielmann, B. and Huthmann, Jens and Koch, Andreas},
      booktitle = {IEEE Proc. 6th Intl. Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)},
      year = {2011},
      organizazion = {IEEE}
    }
    
  66. Mühlbach, S., and Koch, A. (2011). A Scalable Multi-FPGA Platform for Complex Networking Applications. In IEEE 19th Annual Symposium on Field-Programmable Custom Computing Machines (FCCM).
    Preprint
    Bibtex
    @inproceedings{muehlbach2011asmfpgapcna,
      title = {A Scalable Multi-FPGA Platform for Complex Networking Applications},
      author = {Mühlbach, Sascha and Koch, Andreas},
      booktitle = {IEEE 19th Annual Symposium on Field-Programmable Custom Computing Machines (FCCM)},
      year = {2011},
      organizazion = {IEEE}
    }
    
  67. Engel, A., Liebig, B., and Koch, A. (2011). Feasibility Analysis of Reconfigurable Computing in Low-Power Wireless Sensor Applications. In LNCS Proc. 7th International Symposium on Applied Reconfigurable Computing (ARC).
    Preprint
    Bibtex
    @inproceedings{engel2011farclpwsa,
      title = {Feasibility Analysis of Reconfigurable Computing in Low-Power Wireless Sensor Applications},
      author = {Engel, Andreas and Liebig, Björn and Koch, Andreas},
      booktitle = {LNCS Proc. 7th International Symposium on Applied Reconfigurable Computing (ARC)},
      year = {2011},
      organizazion = {LNCS}
    }
    
  68. Mühlbach, S., and Koch, A. (2011). NetStage/DPR: A Self-Adaptable FPGA Platform for Application-Level Network Security. In LNCS Proc. 7th International Symposium on Applied Reconfigurable Computing (ARC).
    Preprint
    Bibtex
    @inproceedings{muehlbach2011nsdprasafpgapalns,
      title = {NetStage/DPR: A Self-Adaptable FPGA Platform for Application-Level Network Security},
      author = {Mühlbach, Sascha and Koch, Andreas},
      booktitle = {LNCS Proc. 7th International Symposium on Applied Reconfigurable Computing (ARC)},
      year = {2011},
      organizazion = {LNCS}
    }
    
  69. Koch, A., Krishnamurthy, R., McAllister, J., Woods, R., and El-Ghazawi, T. (2011). Reconfigurable Computing: Architectures, Tools and Applications. In Lecture Notes in Computer Science 6578.
    Bibtex
    @inproceedings{koch2011rcata,
      title = {Reconfigurable Computing: Architectures, Tools and Applications},
      author = {Koch, Andreas and Krishnamurthy, R. and McAllister, J. and Woods, R. and El-Ghazawi, T.},
      booktitle = {Lecture Notes in Computer Science 6578},
      year = {2011}
    }
    
  70. Lange, H., Wink, T., and Koch, A. (2011). MARC II: A Parametrized Speculative Multi-Ported Memory Subsystem for Reconfigurable Computers. In ACM Proc. Design, Automation, and Test in Europe (DATE).
    Preprint
    Bibtex
    @inproceedings{lange2011marciiapsmpmsrc,
      title = {MARC II: A Parametrized Speculative Multi-Ported Memory Subsystem for Reconfigurable Computers},
      author = {Lange, Holger and Wink, Thorsten and Koch, Andreas},
      booktitle = {ACM Proc. Design, Automation, and Test in Europe (DATE)},
      year = {2011},
      organizazion = {ACM}
    }
    
  71. Mühlbach, S., and Koch, A. (2011). A Novel Network Platform for Secure and Efficient Malware Collection based on Reconfigurable Hardware Logic. In IEEE Proc. World Congress on Internet Security (WorldCIS).
    Preprint
    Bibtex
    @inproceedings{muehlbach2011annpsemcrhl,
      title = {A Novel Network Platform for Secure and Efficient Malware Collection based on Reconfigurable Hardware Logic},
      author = {Mühlbach, Sascha and Koch, Andreas},
      booktitle = {IEEE Proc. World Congress on Internet Security (WorldCIS)},
      year = {2011},
      organizazion = {IEEE}
    }
    
  72. Huthmann, J., Müller, P., Stock, F., Hildenbrand, D., and Koch, A. (2010). Compiling Geometric Algebra Computations into Reconfigurable Hardware Accelerators. In Dagstuhl Seminar Proc. #10281 on Dynamically Reconfigurable Architectures.
    Preprint
    Bibtex
    @inproceedings{huthmann2010cgacrha,
      title = {Compiling Geometric Algebra Computations into Reconfigurable Hardware Accelerators},
      author = {Huthmann, Jens and Müller, Peter and Stock, Florian and Hildenbrand, D. and Koch, Andreas},
      booktitle = {Dagstuhl Seminar Proc. #10281 on Dynamically Reconfigurable Architectures},
      year = {2010}
    }
    
  73. Mühlbach, S., and Koch, A. (2010). A Dynamically Reconfigured Network Platform for High-Speed Malware Collection. In IEEE Proc. Intl. Conf. on ReConFigurable Computing and FPGAs (ReConFig).
    Preprint
    Bibtex
    @inproceedings{muehlbach2010adrnphsmc,
      title = {A Dynamically Reconfigured Network Platform for High-Speed Malware Collection},
      author = {Mühlbach, Sascha and Koch, Andreas},
      booktitle = {IEEE Proc. Intl. Conf. on ReConFigurable Computing and FPGAs (ReConFig)},
      year = {2010},
      organizazion = {IEEE}
    }
    
  74. Stöttinger, M., Huss, S., Mühlbach, S., and Koch, A. (2010). Side-Channel Resistance Evaluation of a Neural Network Based Lightweight Cryptography Scheme. In IEEE Proc. Intl. Conf. on Embedded and Ubiquitous Computing (EUC).
    Preprint
    Bibtex
    @inproceedings{stoettinger2010scrennblcs,
      title = {Side-Channel Resistance Evaluation of a Neural Network Based Lightweight Cryptography Scheme},
      author = {Stöttinger, M. and Huss, S. and Mühlbach, Sascha and Koch, Andreas},
      booktitle = {IEEE Proc. Intl. Conf. on Embedded and Ubiquitous Computing (EUC)},
      year = {2010},
      organizazion = {IEEE}
    }
    
  75. Mühlbach, S., and Koch, A. (2010). An FPGA-based Scalable Platform for High-Speed Malware Collection in Large IP Networks. In IEEE Proc. Intl. Conf. on Field-Programmable Technology (FPT).
    Preprint
    Bibtex
    @inproceedings{muehlbach2010afpgasphsmclipn,
      title = {An FPGA-based Scalable Platform for High-Speed Malware Collection in Large IP Networks},
      author = {Mühlbach, Sascha and Koch, Andreas},
      booktitle = {IEEE Proc. Intl. Conf. on Field-Programmable Technology (FPT)},
      year = {2010},
      organizazion = {IEEE}
    }
    
  76. Lange, H., and Koch, A. (2010). Architectures and Execution Models for Hardware/Software Compilation and their System-Level Realization. In IEEE Transactions on Computers pp. 1363-1377.
    Preprint
    Bibtex
    @inproceedings{lange2010aemhscslr,
      title = {Architectures and Execution Models for Hardware/Software Compilation and their System-Level Realization},
      author = {Lange, Holger and Koch, Andreas},
      booktitle = {IEEE Transactions on Computers pp. 1363-1377},
      year = {2010},
      organizazion = {IEEE}
    }
    
  77. Hempel, G., Hochberger, C., and Koch, A. (2010). A Comparison of Hardware Acceleration Interfaces in a Customizable Soft Core Processor. In IEEE Proc. Intl. Conf. on Field Programmable Logic and Applications (FPL).
    Preprint
    Bibtex
    @inproceedings{hempel2010achaicscp,
      title = {A Comparison of Hardware Acceleration Interfaces in a Customizable Soft Core Processor},
      author = {Hempel, G. and Hochberger, C. and Koch, Andreas},
      booktitle = {IEEE Proc.  Intl. Conf. on Field Programmable Logic and Applications (FPL)},
      year = {2010},
      organizazion = {IEEE}
    }
    
  78. Mühlbach, S., Brunner, M., Roblee, C., and Koch, A. (2010). MalCoBox: Designing a 10 Gb/s Malware Collection Honeypot Using Reconfigurable Technology. In IEEE Proc. Intl. Conf. on Field Programmable Logic and Applications (FPL).
    Preprint
    Bibtex
    @inproceedings{muehlbach2010mcbdgmchurt,
      title = {MalCoBox: Designing a 10 Gb/s Malware Collection Honeypot Using Reconfigurable Technology},
      author = {Mühlbach, Sascha and Brunner, M. and Roblee, C. and Koch, Andreas},
      booktitle = {IEEE Proc.  Intl. Conf. on Field Programmable Logic and Applications (FPL)},
      year = {2010},
      organizazion = {IEEE}
    }
    
  79. Gädke-Lütjens, H., Thielmann, B., and Koch, A. (2010). A Flexible Compute and Memory Infrastructure for High-Level Language to Hardware Compilation. In IEEE Intl. Conf. on Field Programmable Logic and Applications (FPL), Milano (I).
    Preprint Material Material
    Bibtex
    @inproceedings{gaedke-luetjens2010afcmihllhc,
      title = {A Flexible Compute and Memory Infrastructure for High-Level Language to Hardware Compilation},
      author = {Gädke-Lütjens, H. and Thielmann, B. and Koch, Andreas},
      booktitle = {IEEE Intl. Conf. on Field Programmable Logic and Applications (FPL), Milano (I)},
      year = {2010},
      organizazion = {IEEE}
    }
    
  80. Schwinn, C., Hildenbrand, D., Stock, F., and Koch, A. (2010). Gaalop 2.0 - A Geometric Algebra Algorithm Compiler. In Proc. Workshop on Computer Graphics, Computer Vision and Mathematics.
    Preprint
    Bibtex
    @inproceedings{schwinn2010gagaac,
      title = {Gaalop 2.0 - A Geometric Algebra Algorithm Compiler},
      author = {Schwinn, C. and Hildenbrand, D. and Stock, Florian and Koch, Andreas},
      booktitle = {Proc. Workshop on Computer Graphics, Computer Vision and Mathematics},
      year = {2010}
    }
    
  81. Huthmann, J., Müller, P., Stock, F., Hildenbrand, D., and Koch, A. (2010). Accelerating High-Level Engineering Computations by Automatic Compilation of Geometric Algebra to Hardware Accelerators. In IEEE Proc. Intl. Conf. on Embedded Computer Systems: Architectures, MOdeling and Simulation (SAMOS).
    Preprint
    Bibtex
    @inproceedings{huthmann2010ahlecacgaha,
      title = {Accelerating High-Level Engineering Computations by Automatic Compilation of Geometric Algebra to Hardware Accelerators},
      author = {Huthmann, Jens and Müller, Peter and Stock, Florian and Hildenbrand, D. and Koch, Andreas},
      booktitle = {IEEE Proc. Intl. Conf. on Embedded Computer Systems: Architectures, MOdeling and Simulation (SAMOS)},
      year = {2010},
      organizazion = {IEEE}
    }
    
  82. Hildenbrand, D., Pitt, J., and Koch, A. (2010). High Performance Geometric Algebra Computing based on Gaalop. In American Journal of Mathematics: Geometric Algebra Computing for Engineering and Computer Science.
    Preprint
    Bibtex
    @inproceedings{hildenbrand2010hpgacg,
      title = {High Performance Geometric Algebra Computing based on Gaalop},
      author = {Hildenbrand, D. and Pitt, J. and Koch, Andreas},
      booktitle = {American Journal of Mathematics: Geometric Algebra Computing for Engineering and Computer Science},
      year = {2010}
    }
    
  83. Koch, A. (2010). Adaptive Computing Systems and their Design Tools. In Dynamically Reconfigurable Systems.
    Preprint
    Bibtex
    @inproceedings{koch2010acsdt,
      title = {Adaptive Computing Systems and their Design Tools},
      author = {Koch, Andreas},
      booktitle = {Dynamically Reconfigurable Systems},
      year = {2010}
    }
    
  84. Hochberger, C., and Koch, A. (2009). Challenges of Electronic CAD in the Nano Scale Era. In GI LNI Workshop Grand Challenges der technischen Informatik.
    Preprint
    Bibtex
    @inproceedings{hochberger2009cecadnse,
      title = {Challenges of Electronic CAD in the Nano Scale Era},
      author = {Hochberger, C. and Koch, Andreas},
      booktitle = {GI LNI Workshop Grand Challenges der technischen Informatik},
      year = {2009},
      organizazion = {GI}
    }
    
  85. Stock, F., and Koch, A. (2009). A Fast GPU Implementation for Solving Sparse Ill-Posed Linear Equation Systems. In LNCS Proc. of Eighth International Conference on Parallel Processing and Mathematics.
    Preprint The original publication is available at www.spingerlink.com
    Bibtex
    @inproceedings{stock2009afgpuissiples,
      title = {A Fast GPU Implementation for Solving Sparse Ill-Posed Linear Equation Systems},
      author = {Stock, Florian and Koch, Andreas},
      booktitle = {LNCS Proc. of Eighth International Conference on Parallel Processing and Mathematics},
      year = {2009},
      organizazion = {LNCS},
      springer = {http://www.springerlink.com/content/288560u268w77034}
    }
    
  86. Lange, H., Stock, F., Koch, A., and Hildenbrand, D. (2009). Acceleration and Energy Efficiency of a Geometric Algebra Computation using Reconfigurable Computers and GPUs. In IEEE Seventeenth Annual Symposium on Field-Programmable Custom Computing Machines (FCCM).
    Preprint
    Bibtex
    @inproceedings{lange2009aeegacrcgpu,
      title = {Acceleration and Energy Efficiency of a Geometric Algebra Computation using Reconfigurable Computers and GPUs},
      author = {Lange, Holger and Stock, Florian and Koch, Andreas and Hildenbrand, D.},
      booktitle = {IEEE Seventeenth Annual Symposium on Field-Programmable Custom Computing Machines (FCCM)},
      year = {2009},
      organizazion = {IEEE}
    }
    
  87. Lange, H., and Koch, A. (2008). Low-Latency High-Bandwidth HW/SW Communication in a Virtual Memory Environment. In IEEE Intl. Conf. on Field Programmable Logic and Applications (FPL).
    Preprint
    Bibtex
    @inproceedings{lange2008llhbhwswcvme,
      title = {Low-Latency High-Bandwidth HW/SW Communication in a Virtual Memory Environment},
      author = {Lange, Holger and Koch, Andreas},
      booktitle = {IEEE Intl. Conf. on Field Programmable Logic and Applications (FPL)},
      year = {2008},
      organizazion = {IEEE}
    }
    
  88. Gädke, H., Stock, F., and Koch, A. (2008). Memory Access Parallelization in High-Level Language Compilation for Reconfigurable Adaptive Computers. In IEEE Intl. Conf. on Field Programmable Logic and Applications (FPL).
    Preprint
    Bibtex
    @inproceedings{gaedke2008maphllcrac,
      title = {Memory Access Parallelization in High-Level Language Compilation for Reconfigurable Adaptive Computers},
      author = {Gädke, H. and Stock, Florian and Koch, Andreas},
      booktitle = {IEEE Intl. Conf. on Field Programmable Logic and Applications (FPL)},
      year = {2008},
      organizazion = {IEEE}
    }
    
  89. Rekonfigurierbare Architekturen. (2008). In GI Informatik Spektrum.
    Bibtex
    @inproceedings{berekovic2008ra,
      title = {Rekonfigurierbare Architekturen},
      author = {},
      booktitle = {GI Informatik Spektrum},
      year = {2008},
      organizazion = {GI}
    }
    
  90. Gädke, H., and Koch, A. (2008). Accelerating Speculative Execution in High-Level Synthesis with Cancel Tokens. In LNCS Intl. Workshop on Applied Reconfigurable Computing.
    Preprint
    Bibtex
    @inproceedings{gaedke2008asehlsct,
      title = {Accelerating Speculative Execution in High-Level Synthesis with Cancel Tokens},
      author = {Gädke, H. and Koch, Andreas},
      booktitle = {LNCS Intl. Workshop on Applied Reconfigurable Computing},
      year = {2008},
      organizazion = {LNCS}
    }
    
  91. Nagel, W. E., Hoffmann, R., and Koch, A. (2008). Proceedings of the 9th Workshop on Parallel Systems and Algorithms (PASA). In GI Lecture Notes in Informatics No. 124.
    Bibtex
    @inproceedings{nagel2008pwpsapasa,
      title = {Proceedings of the 9th Workshop on Parallel Systems and Algorithms (PASA)},
      author = {Nagel, W. E. and Hoffmann, R. and Koch, Andreas},
      booktitle = {GI Lecture Notes in Informatics No. 124},
      year = {2008},
      organizazion = {GI}
    }
    
  92. Hildenbrand, D., Lange, H., Stock, F., and Koch, A. (2008). Efficient Inverse Kinematics Algorithm based on Conformal Geometric Algebra Using Reconfigurable Hardware. In Intl. Conf. on Computer Graphics Theory and Applications (GRAPP).
    Preprint
    Bibtex
    @inproceedings{hildenbrand2008eikacgaurh,
      title = {Efficient Inverse Kinematics Algorithm based on Conformal Geometric Algebra Using Reconfigurable Hardware},
      author = {Hildenbrand, D. and Lange, Holger and Stock, Florian and Koch, Andreas},
      booktitle = {Intl. Conf. on Computer Graphics Theory and Applications (GRAPP)},
      year = {2008},
      organizazion = {GRAPP}
    }
    
  93. Koch, A. (2008). Datapath Composition. In Reconfigurable Computing.
    Bibtex
    @inproceedings{koch2008dc,
      title = {Datapath Composition},
      author = {Koch, Andreas},
      booktitle = {Reconfigurable Computing},
      year = {2008}
    }
    
  94. Gädke, H., and Koch, A. (2007). Comrade - A Compiler for Adaptive Computing Systems Using a Novel Fast Speculation Technique. In IEEE Intl. Conf. on Field Programmable Logic and Applications (FPL).
    Preprint
    Bibtex
    @inproceedings{gaedke2007cacacsunfst,
      title = {Comrade - A Compiler for Adaptive Computing Systems Using a Novel Fast Speculation Technique},
      author = {Gädke, H. and Koch, Andreas},
      booktitle = {IEEE Intl. Conf. on Field Programmable Logic and Applications (FPL)},
      year = {2007},
      organizazion = {IEEE}
    }
    
  95. Lange, H., and Koch, A. (2007). An Execution Model for Hardware/Software Compilation and its System-Level Realization. In IEEE Intl. Conf. on Field Programmable Logic and Applications (FPL).
    Preprint
    Bibtex
    @inproceedings{lange2007aemhscslr,
      title = {An Execution Model for Hardware/Software Compilation and its System-Level Realization},
      author = {Lange, Holger and Koch, Andreas},
      booktitle = {IEEE Intl. Conf. on Field Programmable Logic and Applications (FPL)},
      year = {2007},
      organizazion = {IEEE}
    }
    
  96. Gädke, H., and Koch, A. (2007). Comrade - A Compiler for Adaptive Systems. In Design, Automation and Test in Europe (DATE), Conference & Exhibition.
    Preprint
    Bibtex
    @inproceedings{gaedke2007cacas,
      title = {Comrade - A Compiler for Adaptive Systems},
      author = {Gädke, H. and Koch, Andreas},
      booktitle = {Design, Automation and Test in Europe (DATE), Conference & Exhibition},
      year = {2007},
      organizazion = {DATE}
    }
    
  97. Platzner, M., Großpietsch, K., Hochberger, C., and Koch, A. (2007). ARCS ’07 - 20th International Conference on Architecture of Computing Systems 2007. In Workshop Proceedings.
    Bibtex
    @inproceedings{platzner2007arcsicacs,
      title = {ARCS '07 - 20th International Conference on Architecture of Computing Systems 2007},
      author = {Platzner, M. and Großpietsch, K. and Hochberger, C. and Koch, Andreas},
      booktitle = {Workshop Proceedings},
      year = {2007},
      organizazion = {ARCS}
    }
    
  98. Lange, H., and Koch, A. (2007). Design and System Level Evaluation of a High Performance Memory System for reconfigurable SoC Platforms. In Proc. HiPEAC Workshop on Reconfigurable Computing.
    Preprint
    Bibtex
    @inproceedings{lange2007dslehpmsscp,
      title = {Design and System Level Evaluation of a High Performance Memory System for reconfigurable SoC Platforms},
      author = {Lange, Holger and Koch, Andreas},
      booktitle = {Proc. HiPEAC Workshop on Reconfigurable Computing},
      year = {2007},
      organizazion = {HiPEAC}
    }
    
  99. Koch, A. (2007). Efficient Integration of Pipelined IP Blocks into Automatically Compiled Datapaths. In EURASIP Journal on Embedded Systems, 2007 Special Issue on Dynamically Reconfigurable Systems.
    Preprint
    Bibtex
    @inproceedings{koch2007eipipbacd,
      title = {Efficient Integration of Pipelined IP Blocks into Automatically Compiled Datapaths},
      author = {Koch, Andreas},
      booktitle = {EURASIP Journal on Embedded Systems, 2007 Special Issue on Dynamically Reconfigurable Systems.},
      year = {2007},
      organizazion = {EURASIP}
    }
    
  100. Koch, A., Leong, P., and Boemo, E. (2006). Proceedings of the 2006 International Conference on Field-Programmable Logic and Applications. In IEEE, 2006.
    Bibtex
    @inproceedings{koch2006picfpla,
      title = {Proceedings of the 2006 International Conference on Field-Programmable Logic and Applications},
      author = {Koch, Andreas and Leong, P. and Boemo, E.},
      booktitle = {IEEE, 2006},
      year = {2006},
      organizazion = {IEEE}
    }
    
  101. Stock, F., and Koch, A. (2006). Architecture Exploration and Tools for Pipelined Coarse-grained Reconfigurable Arrays. In IEEE Intl. Conf. On Field-Programmable Logic (FPL).
    Preprint
    Bibtex
    @inproceedings{stock2006aetpcra,
      title = {Architecture Exploration and Tools for Pipelined Coarse-grained Reconfigurable Arrays},
      author = {Stock, Florian and Koch, Andreas},
      booktitle = {IEEE Intl. Conf. On Field-Programmable Logic (FPL)},
      year = {2006},
      organizazion = {IEEE}
    }
    
  102. Kasprzyk, N., Veen, J. C. van der, and Koch, A. (2005). Configuration Merging for Adaptive Computer Applications. In IEEE Intl. Conf. On Field-Programmable Logic (FPL).
    Preprint
    Bibtex
    @inproceedings{kasprzyk2005cmaca,
      title = {Configuration Merging for Adaptive Computer Applications},
      author = {Kasprzyk, N. and van der Veen, J. C. and Koch, Andreas},
      booktitle = {IEEE Intl. Conf. On Field-Programmable Logic (FPL)},
      year = {2005},
      organizazion = {IEEE}
    }
    
  103. Kasprzyk, N., and Koch, A. (2005). High-Level-Language Compilation for Reconfigurable Computers. In Intl. Conf. on Reconfigurable Communication-centric SoCs.
    Preprint
    Bibtex
    @inproceedings{kasprzyk2005hllcrc,
      title = {High-Level-Language Compilation for Reconfigurable Computers},
      author = {Kasprzyk, N. and Koch, Andreas},
      booktitle = {Intl. Conf. on Reconfigurable Communication-centric SoCs},
      year = {2005}
    }
    
  104. Koch, A. (2004). Advances in Adaptive Computer Technology (habilitation). Tech. Univ. Braunschweig, Germany.
    Preprint
    Bibtex
    @phdthesis{koch2004habil,
      type = {habilitation},
      title = {Advances in Adaptive Computer Technology},
      author = {Koch, Andreas},
      school = {Tech. Univ. Braunschweig, Germany},
      year = {2004},
      organizazion = {Tech. Univ. Braunschweig, Germany}
    }
    
  105. Kasprzyk, N., and Koch, A. (2004). Verbesserte Hardware-Software-Partitionierung für Adaptive Computer. In GI Architecture of Computing Systems (ARCS): Workshop on Dynamically Reconfigurable Systems.
    Preprint
    Bibtex
    @inproceedings{koch2004vhspac,
      title = {Verbesserte Hardware-Software-Partitionierung für Adaptive Computer},
      author = {Kasprzyk, N. and Koch, Andreas},
      booktitle = {GI Architecture of Computing Systems (ARCS): Workshop on Dynamically Reconfigurable Systems},
      year = {2004}
    }
    
  106. Rock, M., and Koch, A. (2004). Architecture-Independent Meta-Optimization by Aggressive Tail Splitting. In LNCS Euro-Par Conference.
    Preprint
    Bibtex
    @inproceedings{koch2004aimoats,
      title = {Architecture-Independent Meta-Optimization by Aggressive Tail Splitting},
      author = {Rock, M. and Koch, Andreas},
      booktitle = {LNCS Euro-Par Conference},
      year = {2004},
      organizazion = {LNCS}
    }
    
  107. Gädke, H., and Koch, A. (2004). Wavelet-based Image Compression on the Reconfigurable Computer ACE-V. In LNCS Intl. Conf. On Field-Programmable Logic (FPL).
    Preprint
    Bibtex
    @inproceedings{koch2004wicrc,
      title = {Wavelet-based Image Compression on the Reconfigurable Computer ACE-V},
      author = {Gädke, H. and Koch, Andreas},
      booktitle = {LNCS Intl. Conf. On Field-Programmable Logic (FPL)},
      year = {2004},
      organizazion = {LNCS}
    }
    
  108. Lange, H., and Koch, A. (2004). Hardware/Software-Codesign by Automatic Embedding of Complex IP Cores. In LNCS Intl. Conf. On Field-Programmable Logic (FPL).
    Preprint
    Bibtex
    @inproceedings{lange2004hscaec,
      title = {Hardware/Software-Codesign by Automatic Embedding of Complex IP Cores},
      author = {Lange, Holger and Koch, Andreas},
      booktitle = {LNCS Intl. Conf. On Field-Programmable Logic (FPL)},
      year = {2004},
      organizazion = {LNCS}
    }
    
  109. Schmidt, C., and Koch, A. (2003). Fast Region Labeling on the Reconfigurable Platform ACE-V. In LNCS Workshop on Field Programmable Logic and Applications.
    Preprint
    Bibtex
    @inproceedings{koch2003frlrp,
      title = {Fast Region Labeling on the Reconfigurable Platform ACE-V},
      author = {Schmidt, C. and Koch, Andreas},
      booktitle = {LNCS Workshop on Field Programmable Logic and Applications},
      year = {2003},
      organizazion = {LNCS}
    }
    
  110. Koch, A. (2003). Compilation for Adaptive Computers: Experiences and Opportunities. In IBFI-Seminar Dynamically Reconfigurable Architectures.
    Preprint
    Bibtex
    @inproceedings{koch2003caceo,
      title = {Compilation for Adaptive Computers: Experiences and Opportunities},
      author = {Koch, Andreas},
      booktitle = {IBFI-Seminar Dynamically Reconfigurable Architectures},
      year = {2003}
    }
    
  111. Kasprzyk, N., Koch, A., Golze, U., and Rock, M. (2003). An Improved Intermediate Representation for Datapath Generation. In International Conference on Engineering of Reconfigurable Systems and Algorithms.
    Preprint
    Bibtex
    @inproceedings{koch2003aiirdg,
      title = {An Improved Intermediate Representation for Datapath Generation},
      author = {Kasprzyk, N. and Koch, Andreas and Golze, U. and Rock, M.},
      booktitle = {International Conference on Engineering of Reconfigurable Systems and Algorithms},
      year = {2003}
    }
    
  112. Koch, A. (2003). Tutorial: Reconfigurable Computing - Fundamentals, Architectures, and Tools. In Conference on Design Automation and Test in Europe (DATE).
    Preprint
    Bibtex
    @inproceedings{koch2003tutorial,
      title = {Tutorial: Reconfigurable Computing - Fundamentals, Architectures, and Tools},
      author = {Koch, Andreas},
      booktitle = {Conference on Design Automation and Test in Europe (DATE)},
      year = {2003}
    }
    
  113. Kasprzyk, N., Koch, A., Golze, U., and Rock, M. (2003). Eine effiziente Kontrollfluss-Repräsentation für die Erzeugung von Datenpfaden. In 11. E.I.S. Workshop.
    Preprint
    Bibtex
    @inproceedings{koch2003ekred,
      title = {Eine effiziente Kontrollfluss-Repräsentation für die Erzeugung von Datenpfaden},
      author = {Kasprzyk, N. and Koch, Andreas and Golze, U. and Rock, M.},
      booktitle = {11. E.I.S. Workshop},
      year = {2003},
      organizazion = {E.I.S.}
    }
    
  114. Koch, A., and Kasprzyk, N. (2002). Module Generators Driving the Compilation for Adaptive Computing Systems. In IEEE International Symposium on FCCMs.
    Bibtex
    @inproceedings{koch2002mgdcacs,
      title = {Module Generators Driving the Compilation for Adaptive Computing Systems},
      author = {Koch, Andreas and Kasprzyk, N.},
      booktitle = {IEEE International Symposium on FCCMs},
      year = {2002},
      organizazion = {IEEE}
    }
    
  115. Koch, A. (2002). Architectures and Tools for Heterogeneous Reconfigurable Systems. In IEEE Workshop on Heterogeneous Reconfigurable Systems-on-Chip.
    Preprint
    Bibtex
    @inproceedings{koch2002athrs,
      title = {Architectures and Tools for Heterogeneous Reconfigurable Systems},
      author = {Koch, Andreas},
      booktitle = {IEEE Workshop on Heterogeneous Reconfigurable Systems-on-Chip},
      year = {2002},
      organizazion = {IEEE}
    }
    
  116. Koch, A. (2002). Compilation for Adaptive Computing Systems Using Complex Parameterized Hardware Objects. In Kluwer Journal of Supercomputing 21 (pp. 179–190).
    Preprint
    Bibtex
    @inproceedings{koch2002cacsucpho,
      title = {Compilation for Adaptive Computing Systems Using Complex Parameterized Hardware Objects},
      author = {Koch, Andreas},
      booktitle = {Kluwer Journal of Supercomputing 21},
      pages = {179--190},
      year = {2002}
    }
    
  117. Neumann, T., and Koch, A. (2001). A Generic Library for Adaptive Computing Environments. In LNCS Workshop on Field-Programmable Logic and Applications, Belfast, 08-2001.
    Preprint
    Bibtex
    @inproceedings{koch2001aglace,
      title = {A Generic Library for Adaptive Computing Environments},
      author = {Neumann, T. and Koch, Andreas},
      booktitle = {LNCS Workshop on Field-Programmable Logic and Applications, Belfast, 08-2001.},
      year = {2001},
      organizazion = {LNCS}
    }
    
  118. Kasprzyk, N., and Koch, A. (2001). Advances in Compiler Construction for Adaptive Computers. In International Conference on Parallel and Distributed Processing Techniques and Applications.
    Preprint
    Bibtex
    @inproceedings{koch2001accac,
      title = {Advances in Compiler Construction for Adaptive Computers},
      author = {Kasprzyk, N. and Koch, Andreas},
      booktitle = {International Conference on Parallel and Distributed Processing Techniques and Applications},
      year = {2001}
    }
    
  119. Koch, A. (2001). Adaptive Rechensysteme und ihre Entwurfswerkzeuge. In 10. E.I.S.-Workshop.
    Preprint
    Bibtex
    @inproceedings{koch2001are,
      title = {Adaptive Rechensysteme und ihre Entwurfswerkzeuge},
      author = {Koch, Andreas},
      booktitle = {10. E.I.S.-Workshop},
      year = {2001},
      organizazion = {E.I.S.}
    }
    
  120. Lange, H., and Koch, A. (2000). Memory Access Schemes for Configurable Processors. In LNCS Intl. Workshop on Field-Programmable Logic and Applications.
    Preprint
    Bibtex
    @inproceedings{koch2000mascp,
      title = {Memory Access Schemes for Configurable Processors},
      author = {Lange, Holger and Koch, Andreas},
      booktitle = {LNCS Intl. Workshop on Field-Programmable Logic and Applications},
      year = {2000},
      organizazion = {LNCS}
    }
    
  121. Koch, A. (2000). Creation and Embedding of Complex Parameterized Hardware Objects. In LNCS Workshop on Engineering of Reconfigurable Hardware/Software Objects.
    Preprint
    Bibtex
    @inproceedings{koch2000cecpho,
      title = {Creation and Embedding of Complex Parameterized Hardware Objects},
      author = {Koch, Andreas},
      booktitle = {LNCS Workshop on Engineering of Reconfigurable Hardware/Software Objects},
      year = {2000},
      organizazion = {LNCS}
    }
    
  122. Koch, A. (2000). A Comprehensive Prototyping Platform for Hardware-Software Codesign. In IEEE Workshop on Rapid Systems Prototyping.
    Preprint
    Bibtex
    @inproceedings{koch2000hsc,
      title = {A Comprehensive Prototyping Platform for Hardware-Software Codesign},
      author = {Koch, Andreas},
      booktitle = {IEEE Workshop on Rapid Systems Prototyping},
      year = {2000},
      organizazion = {IEEE}
    }
    
  123. Koch, A. (1999). Adaptive Rechensysteme - Architekturen und Werkzeuge. In 9. E.I.S.-Workshop.
    Preprint
    Bibtex
    @inproceedings{koch1999arauw,
      title = {Adaptive Rechensysteme - Architekturen und Werkzeuge.},
      author = {Koch, Andreas},
      booktitle = {9. E.I.S.-Workshop},
      year = {1999},
      organizazion = {E.I.S.}
    }
    
  124. Koch, A. (1999). On Tool Integration in High-Performance FPGA Design Flows. In LNCS Intl. Workshop on Field-Programmable Logic and Applications.
    Preprint
    Bibtex
    @inproceedings{koch1999hpfpga,
      title = {On Tool Integration in High-Performance FPGA Design Flows},
      author = {Koch, Andreas},
      booktitle = {LNCS Intl. Workshop on Field-Programmable Logic and Applications},
      year = {1999},
      organizazion = {LNCS}
    }
    
  125. Boege, M., and Koch, A. (1999). A Processor for Artificial Life Simulation. In LNCS Intl. Workshop on Field-Programmable Logic and Applications.
    Preprint
    Bibtex
    @inproceedings{koch1999als,
      title = {A Processor for Artificial Life Simulation},
      author = {Boege, M. and Koch, Andreas},
      booktitle = {LNCS Intl. Workshop on Field-Programmable Logic and Applications},
      year = {1999},
      organizazion = {LNCS}
    }
    
  126. Koch, A. (1999). Enabling Automatic Module Generation for FCCM Compilers. In IEEE Intl. Symposium on FCCMs.
    Preprint
    Bibtex
    @inproceedings{koch1999fccm,
      title = {Enabling Automatic Module Generation for FCCM Compilers},
      author = {Koch, Andreas},
      booktitle = {IEEE Intl. Symposium on FCCMs},
      year = {1999},
      organizazion = {IEEE}
    }
    
  127. Koch, A. (1999). Unified Access to Heterogeneous Module Generators. In Intl. Symposium on FPGAs.
    Bibtex
    @inproceedings{koch1999hmg,
      title = {Unified Access to Heterogeneous Module Generators},
      author = {Koch, Andreas},
      booktitle = {Intl. Symposium on FPGAs},
      year = {1999},
      organizazion = {ACM}
    }
    
  128. Koch, A. (1998). Generator-based Design Flows for Reconfigurable Computing: A Tutorial on Tool Integration using FLAME. In PACT98 Workshop on Reconfigurable Computing.
    Preprint
    Bibtex
    @inproceedings{koch1998rcflame,
      title = {Generator-based Design Flows for Reconfigurable Computing: A Tutorial on Tool Integration using FLAME},
      author = {Koch, Andreas},
      booktitle = {PACT98 Workshop on Reconfigurable Computing},
      year = {1998},
      organizazion = {PACT}
    }
    
  129. Koch, A. (1998). Accessing Module Libraries (Talk). In ACS Principal Investigator Conference, Napa Valley (CA, USA), 04-1998.
    Bibtex
    @inproceedings{koch1998aml,
      title = {Accessing Module Libraries (Talk)},
      author = {Koch, Andreas},
      booktitle = {ACS Principal Investigator Conference, Napa Valley (CA, USA), 04-1998.},
      year = {1998}
    }
    
  130. Koch, A. (1998). Proposal for inter-tool communication protocols in the ACS/NC System (Talk). In Synopsys Inc., Mountain View (CA, USA), 04-1998.
    Bibtex
    @inproceedings{koch1998intertool,
      title = {Proposal for inter-tool communication protocols in the ACS/NC System (Talk)},
      author = {Koch, Andreas},
      booktitle = {Synopsys Inc., Mountain View (CA, USA), 04-1998.},
      year = {1998}
    }
    
  131. Koch, A. (1998). Efficient Datapath Composition for Coarse-Grained FPGAs (Talk). In Xilinx Inc., San Jose (CA, USA), 04-1998.
    Bibtex
    @inproceedings{koch1998cgfpga,
      title = {Efficient Datapath Composition for Coarse-Grained FPGAs (Talk)},
      author = {Koch, Andreas},
      booktitle = {Xilinx Inc., San Jose (CA, USA), 04-1998.},
      year = {1998}
    }
    
  132. Koch, A. (1998). FLAME - A Flexible API for Module-based Environments (Talk). In 2nd ACS Project Review, Berkeley (CA, USA), 03-1998.
    Preprint
    Bibtex
    @inproceedings{koch1998flame,
      title = {FLAME - A Flexible API for Module-based Environments (Talk)},
      author = {Koch, Andreas},
      booktitle = {2nd ACS Project Review, Berkeley (CA, USA), 03-1998.},
      year = {1998}
    }
    
  133. Koch, A. (1998). Regular Datapaths on Field-Programmable Gate Arrays (Talk). In 3rd BRASS/IRAM Industrial Feedback Retreat.
    Preprint
    Bibtex
    @inproceedings{koch1998fpga,
      title = {Regular Datapaths on Field-Programmable Gate Arrays (Talk)},
      author = {Koch, Andreas},
      booktitle = {3rd BRASS/IRAM Industrial Feedback Retreat},
      year = {1998}
    }
    
  134. Koch, A. (1997). Practical Experiences with the SPARXIL Co-Processor. In IEEE 31st Asilomar Conference on Signals, Systems, and Computers.
    Preprint
    Bibtex
    @inproceedings{koch1997sparxil,
      title = {Practical Experiences with the SPARXIL Co-Processor},
      author = {Koch, Andreas},
      booktitle = {IEEE 31st Asilomar Conference on Signals, Systems, and Computers},
      year = {1997},
      organizazion = {IEEE}
    }
    
  135. Koch, A. (1997). Regular Datapaths on Field-Programmable Gate Arrays (dissertation). Tech. Univ. Braunschweig (Germany).
    Preprint
    Bibtex
    @phdthesis{koch1997diss,
      type = {dissertation},
      title = {Regular Datapaths on Field-Programmable Gate Arrays},
      author = {Koch, Andreas},
      school = {Tech. Univ. Braunschweig (Germany)},
      year = {1997},
      organizazion = {Tech. Univ. Braunschweig (Germany)}
    }
    
  136. Koch, A. (1997). Objekt-orientierte Modellierung von hybriden Hardware- Software-Systemen am Beispiel des "European Home System" (EHS) Standards. In 8. E.I.S. Workshop.
    Preprint
    Bibtex
    @inproceedings{koch1997oo,
      title = {Objekt-orientierte Modellierung von hybriden Hardware- Software-Systemen am Beispiel des "European Home System" (EHS) Standards.},
      author = {Koch, Andreas},
      booktitle = {8. E.I.S. Workshop},
      year = {1997},
      organizazion = {E.I.S.}
    }
    
  137. Koch, A. (1996). Module Compaction in FPGA-based Regular Datapaths. In 33rd Design Automation Conference (DAC).
    Preprint
    Bibtex
    @inproceedings{koch1996datapaths2,
      title = {Module Compaction in FPGA-based Regular Datapaths},
      author = {Koch, Andreas},
      booktitle = {33rd Design Automation Conference (DAC)},
      year = {1996},
      organizazion = {ACM}
    }
    
  138. Koch, A. (1996). Structured Design Implementation - A Strategy for Implementing Regular Datapaths on FPGAs. In 4th International Symposium on FPGAs (FPGA).
    Preprint
    Bibtex
    @inproceedings{koch1996datapaths,
      title = {Structured Design Implementation - A Strategy for Implementing Regular Datapaths on FPGAs},
      author = {Koch, Andreas},
      booktitle = {4th International Symposium on FPGAs (FPGA)},
      year = {1996},
      organizazion = {ACM}
    }
    
  139. Koch, A. (1995). Effiziente Implementierung von Datenpfaden auf FPGAs. In 7. E.I.S. Workshop.
    Preprint
    Bibtex
    @inproceedings{koch1995effizient,
      title = {Effiziente Implementierung von Datenpfaden auf FPGAs},
      author = {Koch, Andreas},
      booktitle = {7. E.I.S. Workshop},
      year = {1995},
      organizazion = {E.I.S.}
    }
    
  140. Koch, A. (1995). Structured Design Implementation - Eine Implementierungsstrategie für Datenpfade auf FPGAs. In GI/ITG Workshop "Anwenderprogrammierbare Schaltungen".
    Preprint
    Bibtex
    @inproceedings{koch1995datenpfade,
      title = {Structured Design Implementation - Eine Implementierungsstrategie für Datenpfade auf FPGAs},
      author = {Koch, Andreas},
      booktitle = {GI/ITG Workshop "Anwenderprogrammierbare Schaltungen"},
      year = {1995},
      organizazion = {GI/ITG}
    }
    
  141. Koch, A. (1994). A Universal Co-Processor for Workstations. In More FPGAs.
    Preprint
    Bibtex
    @inproceedings{koch1994universal,
      title = {A Universal Co-Processor for Workstations},
      author = {Koch, Andreas},
      booktitle = {More FPGAs},
      year = {1994}
    }
    
  142. Koch, A. (1994). User-friendly FPGA Design with an Improved Cadence Opus - Xilinx XACT Interface. In 5th EUROCHIP Workshop.
    Preprint
    Bibtex
    @inproceedings{koch1994cadence,
      title = {User-friendly FPGA Design with an Improved Cadence Opus - Xilinx XACT Interface},
      author = {Koch, Andreas},
      booktitle = {5th EUROCHIP Workshop},
      year = {1994},
      organizazion = {EUROCHIP}
    }
    
  143. Koch, A. (1994). SPARXIL: Ein konfigurierbarer FPGA-Coprozessor. In GI/ITG Workshop "Arch. für hochintegrierte Schaltungen".
    Preprint
    Bibtex
    @inproceedings{koch1994copro,
      title = {SPARXIL: Ein konfigurierbarer FPGA-Coprozessor},
      author = {Koch, Andreas},
      booktitle = {GI/ITG Workshop "Arch. für hochintegrierte Schaltungen"},
      year = {1994},
      organizazion = {GI/ITG}
    }
    
  144. Koch, A. (1993). An FPGA-based Co-Processor for SBus Workstations. In LNCS Proc. 3rd Conference on Field Programmable Logic and Applications (FPL). LNCS.
    Preprint
    Bibtex
    @inproceedings{koch1993copro,
      title = {An FPGA-based Co-Processor for SBus Workstations},
      author = {Koch, Andreas},
      booktitle = {LNCS Proc. 3rd Conference on Field Programmable Logic and Applications (FPL)},
      year = {1993},
      organization = {LNCS}
    }
    
  145. Koch, A. (1993). FPGA Applications in Education and Research. In 4rd EUROCHIP Workshop (pp. 260–265).
    Preprint
    Bibtex
    @inproceedings{koch1993app,
      title = {FPGA {A}pplications in {E}ducation and {R}esearch},
      author = {Koch, Andreas},
      booktitle = {4rd {EUROCHIP} {W}orkshop},
      pages = {260--265},
      year = {1993}
    }
    
  146. Koch, A. (1992). Experiences with the Framework Cadence Skill/IL. In Proc. 3rd EUROCHIP Workshop (pp. 118–123). EUROCHIP.
    Preprint
    Bibtex
    @inproceedings{koch1992exp,
      title = {Experiences with the {F}ramework {C}adence {S}kill/{IL}},
      author = {Koch, Andreas},
      booktitle = {Proc. 3rd {EUROCHIP} {W}orkshop},
      pages = {118--123},
      year = {1992},
      organization = {EUROCHIP}
    }
    
  147. Koch, A. (1992). Integrationssprachen in VLSI-Design-Frameworks am Beispiel von Cadence Skill/IL (Master's thesis). TU Braunschweig.
    Bibtex
    @mastersthesis{koch1992diplom,
      title = {Integrationssprachen in {VLSI}-{D}esign-{F}rameworks am {B}eispiel von {C}adence {S}kill/{IL}},
      author = {Koch, Andreas},
      year = {1992},
      school = {TU {B}raunschweig}
    }