Prof. Dr-Ing. Andreas Koch
- Technische Universität Darmstadt
- Computer Science Department (FB20)
- Embedded Systems & Applications Group (ESA)
- Hochschulstr. 10
- D-64289 Darmstadt
- Phone: +49 6151 / 16-22420
- Fax: +49 6151 / 16-22422
- E-Mail: koch@esa.tu-darmstadt.de
- S2|02 Raum E101
Forschungsgebiete
Andreas Koch befasst sich schwerpunktmäßig mit adaptiven Rechensystemen. Es handelt sich dabei um Computer, bei denen auch die Hardware in Teilaspekten dynamisch an die Erfordernisse der gerade ablaufenden Software angepasst werden kann. Die Palette der einzelnen Arbeitsgebiete reicht dabei von der Entwicklung geeigneter CAD-Werkzeuge (spezialisierte Compiler und Chip-Layoutwerkzeuge) über die Konzeption von Rechnerarchitekturen bis hin zum praktischen Aufbau und der Erprobung von Prototypensystemen. Daneben ist Herr Koch auch an objektorientierten Programmiersprachen und Software-Engineering interessiert.
Lebenslauf
- 2005
Habilitation und Ruf an die TU Darmstadt
- 1999
Post-Doktorand (TU Braunschweig, EIS)
- 1997-1999
Post-Doktorand (UC Berkeley, Arbeitsgruppe BRASS)
- 1997
Promotion zum Dr.-Ing. (TU Braunschweig, EIS)
- 1992
Diplom in Informatik (TU Braunschweig)
Publications
- Oppermann, J., Damian-Kosterhon, B. M., Meisel, F., Mürmann, T., Müller, P., Jentzsch, E., and Koch, A. (2024, October). Longnail: Hardware Synthesis of CoreDSL Custom Instructions for MCU- and Application-Class Cores. Poster presented at RISC-V Summit North America 2024.
PosterBibtex
@misc{meiselMuermann2024RVSummit, title = {Longnail: Hardware Synthesis of CoreDSL Custom Instructions for MCU- and Application-Class Cores}, author = {Oppermann, Julian and Damian-Kosterhon, Brindusa Mihaela and Meisel, Florian and M\"{u}rmann, Tammo and M\"{u}ller, Philipp and Jentzsch, Eyck and Koch, Andreas}, howpublished = {Poster presented at RISC-V Summit North America 2024}, year = {2024}, month = oct, location = {Santa Clara, CA, USA} }
- Meisel, F., Spang, C., Volz, D., and Koch, A. (2024). TaPaFuzz: Hardware-accelerated RISC-V bare-metal firmware fuzzing using rapid job launches. Journal of Systems Architecture. doi: https://doi.org/10.1016/j.sysarc.2024.103288
DOI URLBibtex
@article{meisel2024JSA, title = {TaPaFuzz: Hardware-accelerated RISC-V bare-metal firmware fuzzing using rapid job launches}, journal = {Journal of Systems Architecture}, year = {2024}, issn = {1383-7621}, doi = {https://doi.org/10.1016/j.sysarc.2024.103288}, url = {https://www.sciencedirect.com/science/article/pii/S138376212400225X}, author = {Meisel, Florian and Spang, Christoph and Volz, David and Koch, Andreas}, note = {Open access available shortly}, keywords = {Fuzzing, RISC-V, Coverage, Security, FPGA} }
- Khan, B., and Koch, A. (2024). DeLiBA-K: Speeding-up Hardware-Accelerated Distributed Storage Access by Tighter Linux Kernel Integration and Use of a Modern API. In Proceedings of the SC ’24 Workshops of The International Conference on High Performance Computing, Network, Storage, and Analysis.
PreprintBibtex
@inproceedings{khan2024H2RC, author = {Khan, Babar and Koch, Andreas}, booktitle = {Proceedings of the SC ’24 Workshops of The International Conference on High Performance Computing, Network, Storage, and Analysis}, title = {DeLiBA-K: Speeding-up Hardware-Accelerated Distributed Storage Access by Tighter Linux Kernel Integration and Use of a Modern API}, year = {2024} }
- Kalkhof, T., and Koch, A. (2024). Speeding-Up LULESH on HPX: Useful Tricks and Lessons Learned using a Many-Task-Based Approach. In Proceedings of the SC ’24 Workshops of The International Conference on High Performance Computing, Network, Storage, and Analysis.
PreprintBibtex
@inproceedings{kalkhof2024pawatm, author = {Kalkhof, Torben and Koch, Andreas}, booktitle = {Proceedings of the SC ’24 Workshops of The International Conference on High Performance Computing, Network, Storage, and Analysis}, title = {Speeding-Up LULESH on HPX: Useful Tricks and Lessons Learned using a Many-Task-Based Approach}, year = {2024} }
- Heinz, C., and Koch, A. (2024). COSSEA: Context-based SoC Security Enforcement Architecture. In 2024 IEEE 37th International System-on-Chip Conference (SOCC). doi: 10.1109/SOCC62300.2024.10737786
Preprint DOIBibtex
@inproceedings{heinz2024socc, author = {Heinz, Carsten and Koch, Andreas}, booktitle = {2024 IEEE 37th International System-on-Chip Conference (SOCC)}, title = {COSSEA: Context-based SoC Security Enforcement Architecture}, year = {2024}, doi = {10.1109/SOCC62300.2024.10737786} }
- Bernardo, P. P., Schmid, P., Bringmann, O., Iftekhar, M., Sadiye, B., Mueller, W., Koch, A., et al. (2024). A Scalable RISC-V Hardware Platform for Intelligent Sensor Processing. In 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE) (pp. 1–5).
Preprint DOIBibtex
@inproceedings{koch2024date, author = {Bernardo, Paul Palomero and Schmid, Patrick and Bringmann, Oliver and Iftekhar, Mohammed and Sadiye, Babak and Mueller, Wolfgang and Koch, Andreas and Jentzsch, Eyck and Sauer, Axel and Feldner, Ingo and Ecker, Wolfgang}, booktitle = {2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)}, title = {A Scalable RISC-V Hardware Platform for Intelligent Sensor Processing}, year = {2024}, volume = {}, number = {}, pages = {1-5}, keywords = {Event detection;Image edge detection;Neural networks;Ecosystems;Hardware;Real-time systems;Phase locked loops;RISC-V;AI;IoT;edge applications;ecosystem}, doi = {} }
- Oppermann, J., Damian-Kosterhon, B. M., Meisel, F., Mürmann, T., Jentzsch, E., and Koch, A. (2024). Longnail: High-Level Synthesis of Portable Custom Instruction Set Extensions for RISC-V Processors from Descriptions in the Open-Source CoreDSL Language. In Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 3, ASPLOS ’24 (pp. 591–606). New York, NY, USA: Association for Computing Machinery. doi: 10.1145/3620666.3651375
DOI URL PosterBibtex
@inproceedings{oppermann2024asplos, author = {Oppermann, Julian and Damian-Kosterhon, Brindusa Mihaela and Meisel, Florian and M\"{u}rmann, Tammo and Jentzsch, Eyck and Koch, Andreas}, title = {Longnail: High-Level Synthesis of Portable Custom Instruction Set Extensions for RISC-V Processors from Descriptions in the Open-Source CoreDSL Language}, year = {2024}, isbn = {9798400703867}, publisher = {Association for Computing Machinery}, address = {New York, NY, USA}, url = {https://doi.org/10.1145/3620666.3651375}, note = {Open Access}, doi = {10.1145/3620666.3651375}, booktitle = {Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 3}, pages = {591–606}, numpages = {16}, location = {, La Jolla, CA, USA, }, series = {ASPLOS '24} }
- Tamimi, S., Bernhardt, A., Stock, F., Petrov, I., and Koch, A. (2024). DANSEN: Database Acceleration on Native Computational Storage by Exploiting NDP. ACM Trans. Reconfigurable Technol. Syst. New York, NY, USA: Association for Computing Machinery. doi: 10.1145/3655625
DOI URLBibtex
@article{tamimi2024trets, author = {Tamimi, Sajjad and Bernhardt, Arthur and Stock, Florian and Petrov, Ilia and Koch, Andreas}, title = {DANSEN: Database Acceleration on Native Computational Storage by Exploiting NDP}, year = {2024}, publisher = {Association for Computing Machinery}, address = {New York, NY, USA}, issn = {1936-7406}, url = {https://doi.org/10.1145/3655625}, doi = {10.1145/3655625}, note = {Just Accepted}, journal = {ACM Trans. Reconfigurable Technol. Syst.}, month = apr, keywords = {Near-Data Processing, Computational Storage, FPGA, Database Management Systems.} }
- Jasny, M., Thostrup, L., Tamimi, S., Koch, A., István, Z., and Binnig, C. (2024). Zero-sided RDMA: Network-driven Data Shuffling for Disaggregated Heterogeneous Cloud DBMSs. Proc. ACM Manag. Data, 2(1). New York, NY, USA: Association for Computing Machinery. doi: 10.1145/3639291
DOI URLBibtex
@article{Jasny2024SIGMOD, author = {Jasny, Matthias and Thostrup, Lasse and Tamimi, Sajjad and Koch, Andreas and Istv\'{a}n, Zsolt and Binnig, Carsten}, title = {Zero-sided RDMA: Network-driven Data Shuffling for Disaggregated Heterogeneous Cloud DBMSs}, year = {2024}, issue_date = {February 2024}, publisher = {Association for Computing Machinery}, address = {New York, NY, USA}, volume = {2}, number = {1}, url = {https://doi.org/10.1145/3639291}, doi = {10.1145/3639291}, journal = {Proc. ACM Manag. Data}, month = mar, articleno = {36}, numpages = {28}, keywords = {FPGA, GPU, RDMA, communication scheme, heterogeneous compute} }
- Heinz, C., Kalkhof, T., Lavan, Y., and Koch, A. (2024). TaPaSCo-AIE: An Open-Source Framework for Streaming-based Heterogeneous Acceleration using AMD AI Engines. In 2024 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW). doi: 10.1109/IPDPSW63119.2024.00041
Best Paper Award Preprint DOIBibtex
@inproceedings{heinz2024raw, author = {Heinz, Carsten and Kalkhof, Torben and Lavan, Yannick and Koch, Andreas}, booktitle = {2024 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)}, title = {TaPaSCo-AIE: An Open-Source Framework for Streaming-based Heterogeneous Acceleration using AMD AI Engines}, year = {2024}, doi = {10.1109/IPDPSW63119.2024.00041} }
- Kalkhof, T., Heinz, C., and Koch, A. (2024). Enabling FPGA and AI Engine Tasks in the HPX Programming Framework for Heterogeneous High-Performance Computing. In Applied Reconfigurable Computing. Architectures, Tools, and Applications. Springer International Publishing. doi: 10.1007/978-3-031-55673-9_6
Preprint DOIBibtex
@inproceedings{kalkhof2024arc, author = {Kalkhof, Torben and Heinz, Carsten and Koch, Andreas}, title = {Enabling FPGA and AI Engine Tasks in the HPX Programming Framework for Heterogeneous High-Performance Computing}, booktitle = {Applied Reconfigurable Computing. Architectures, Tools, and Applications}, year = {2024}, publisher = {Springer International Publishing}, doi = {10.1007/978-3-031-55673-9_6} }
- Strobl, J., Solis-Vasquez, L., Lavan, Y., and Koch, A. (2024). Graphtoy: Fast Software Simulation of Applications for AMD’s AI Engines. In Applied Reconfigurable Computing. Architectures, Tools, and Applications. Springer International Publishing. doi: 10.1007/978-3-031-55673-9_12
Preprint DOI SlidesBibtex
@inproceedings{strobl2024arc, author = {Strobl, Jonathan and Solis-Vasquez, Leonardo and Lavan, Yannick and Koch, Andreas}, title = {Graphtoy: Fast Software Simulation of Applications for AMD’s AI Engines}, booktitle = {Applied Reconfigurable Computing. Architectures, Tools, and Applications}, year = {2024}, publisher = {Springer International Publishing}, doi = {10.1007/978-3-031-55673-9_12} }
- Kaushanski, S., Wirth, J., Jentzsch, E., and Koch, A. (2023). Accelerating Complex System Simulation using Parallel SystemC and FPGAs. 2023 Design and Verification Conference in Europe (DVCon Europe).
PreprintBibtex
@article{kaushanski2023dvcon, author = {Kaushanski, Stanislaw and Wirth, Johannes and Jentzsch, Eyck and Koch, Andreas}, title = {Accelerating Complex System Simulation using Parallel SystemC and FPGAs}, year = {2023}, booktitle = {2023 Design and Verification Conference in Europe (DVCon Europe)} }
- Bernhardt, A., Koch, A., and Petrov, I. (2023). PimDB: From Main-Memory DBMS to Processing-In-Memory DBMS-Engines on Intelligent Memories. In Proceedings of the 19th International Workshop on Data Management on New Hardware, DaMoN ’23 (pp. 44–52). New York, NY, USA: Association for Computing Machinery. doi: 10.1145/3592980.3595312
DOI URLBibtex
@inproceedings{10.1145/3592980.3595312, author = {Bernhardt, Arthur and Koch, Andreas and Petrov, Ilia}, title = {PimDB: From Main-Memory DBMS to Processing-In-Memory DBMS-Engines on Intelligent Memories}, year = {2023}, isbn = {9798400701917}, publisher = {Association for Computing Machinery}, address = {New York, NY, USA}, url = {https://doi.org/10.1145/3592980.3595312}, doi = {10.1145/3592980.3595312}, booktitle = {Proceedings of the 19th International Workshop on Data Management on New Hardware}, pages = {44–52}, numpages = {9}, location = {, Seattle, WA, USA, }, series = {DaMoN '23} }
- Weckert, C., Solis-Vasquez, L., Oppermann, J., Koch, A., and Sinnen, O. (2023). Altis-SYCL: Migrating Altis Benchmarking Suite from CUDA to SYCL for GPUs and FPGAs. In Proceedings of the SC ’23 Workshops of The International Conference on High Performance Computing, Network, Storage, and Analysis. Association for Computing Machinery. doi: 10.1145/3624062.3624542
Preprint DOI SlidesBibtex
@inproceedings{weckert2023h2rc, author = {Weckert, Christoph and Solis-Vasquez, Leonardo and Oppermann, Julian and Koch, Andreas and Sinnen, Oliver}, title = {Altis-SYCL: Migrating Altis Benchmarking Suite from CUDA to SYCL for GPUs and FPGAs}, booktitle = {Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, Network, Storage, and Analysis}, year = {2023}, publisher = {Association for Computing Machinery}, doi = {10.1145/3624062.3624542} }
- Tamimi, S., Stock, F., Bernhardt, A., Petrov, I., and Koch, A. (2023). NVMulator: A Configurable Open-Source Non-volatile Memory Emulator for FPGAs. In Applied Reconfigurable Computing. Architectures, Tools, and Applications. Springer International Publishing. doi: 10.1007/978-3-031-42921-7_3
DOI URLBibtex
@inproceedings{tamimi2023arc, author = {Tamimi, Sajjad and Stock, Florian and Bernhardt, Arthur and Petrov, Ilia and Koch, Andreas}, title = {NVMulator: A Configurable Open-Source Non-volatile Memory Emulator for FPGAs}, booktitle = {Applied Reconfigurable Computing. Architectures, Tools, and Applications}, year = {2023}, publisher = {Springer International Publishing}, url = {https://doi.org/10.1007/978-3-031-42921-7_3}, doi = {10.1007/978-3-031-42921-7_3} }
- Khan, B., Heinz, C., and Koch, A. (2023). The Open-Source DeLiBA2 Hardware/Software Framework for Distributed Storage Accelerators. ACM Trans. Reconfigurable Technol. Syst. New York, NY, USA: Association for Computing Machinery. doi: 10.1145/3624482
Preprint DOI URLBibtex
@article{khan2023TRETS, author = {Khan, Babar and Heinz, Carsten and Koch, Andreas}, title = {The Open-Source DeLiBA2 Hardware/Software Framework for Distributed Storage Accelerators}, year = {2023}, publisher = {Association for Computing Machinery}, address = {New York, NY, USA}, issn = {1936-7406}, url = {https://doi.org/10.1145/3624482}, doi = {10.1145/3624482}, note = {Just Accepted}, journal = {ACM Trans. Reconfigurable Technol. Syst.}, month = sep, keywords = {Application and Architecture, FPGA architecture, Programming Tools, Open-Source, High-Level Synthesis, Linux, FPGA acceleration} }
- Volz, D., Koch, A., and Bloessl, B. (2023). Software-Defined Wireless Communication Systems for Heterogeneous Architectures. In Proceedings of the 29th Annual International Conference on Mobile Computing and Networking, ACM MobiCom ’23. New York, NY, USA: Association for Computing Machinery. doi: 10.1145/3570361.3614084
Preprint DOI URLBibtex
@inproceedings{volz2023mobicom, author = {Volz, David and Koch, Andreas and Bloessl, Bastian}, title = {Software-Defined Wireless Communication Systems for Heterogeneous Architectures}, year = {2023}, isbn = {9781450399906}, publisher = {Association for Computing Machinery}, address = {New York, NY, USA}, url = {https://doi.org/10.1145/3570361.3614084}, doi = {10.1145/3570361.3614084}, booktitle = {Proceedings of the 29th Annual International Conference on Mobile Computing and Networking}, articleno = {110}, numpages = {3}, location = {Madrid, Spain}, series = {ACM MobiCom '23} }
- Heinz, C., and Koch, A. (2023). DD-MPU: Dynamic and Distributed Memory Protection Unit for Embedded System-on-Chips. In Intl. Conf. on Embedded Computer Systems: Architectures, MOdeling and Simulation (SAMOS). Springer Nature Switzerland. doi: 10.1007/978-3-031-46077-7_19
Preprint DOIBibtex
@inproceedings{heinz2023samos, title = {DD-MPU: Dynamic and Distributed Memory Protection Unit for Embedded System-on-Chips}, author = {Heinz, Carsten and Koch, Andreas}, booktitle = {Intl. Conf. on Embedded Computer Systems: Architectures, MOdeling and Simulation (SAMOS)}, year = {2023}, publisher = {Springer Nature Switzerland}, doi = {10.1007/978-3-031-46077-7_19} }
- Solis-Vasquez, L., Mascarenhas, E., and Koch, A. (2023). Experiences Migrating CUDA to SYCL: A Molecular Docking Case Study. In Proceedings of the 2023 International Workshop on OpenCL. Association for Computing Machinery. doi: 10.1145/3585341.3585372
Preprint DOI SlidesBibtex
@inproceedings{solis2023iwocl, author = {Solis-Vasquez, Leonardo and Mascarenhas, Edward and Koch, Andreas}, title = {Experiences Migrating CUDA to SYCL: A Molecular Docking Case Study}, booktitle = {Proceedings of the 2023 International Workshop on OpenCL}, year = {2023}, publisher = {Association for Computing Machinery}, doi = {10.1145/3585341.3585372} }
- Solis-Vasquez, L., Focht, E., and Koch, A. (2023). Simulating Molecular Docking on the SX-Aurora TSUBASA Vector Engine. In M. M. Resch, J. Gebert, H. Kobayashi, and W. Bez (Eds.), Sustained Simulation Performance 2021 (pp. 21–35). Springer International Publishing. doi: 10.1007/978-3-031-18046-0_2
DOI SlidesBibtex
@inproceedings{solis2023wssp, author = {Solis-Vasquez, Leonardo and Focht, Erich and Koch, Andreas}, editor = {Resch, Michael M. and Gebert, Johannes and Kobayashi, Hiroaki and Bez, Wolfgang}, title = {Simulating Molecular Docking on the SX-Aurora TSUBASA Vector Engine}, booktitle = {Sustained Simulation Performance 2021}, year = {2023}, publisher = {Springer International Publishing}, pages = {21--35}, doi = {10.1007/978-3-031-18046-0_2}, slides = {https://sx-aurora.github.io/posts/Molecular-Docking-Simulation} }
- Meisel, F., Volz, D., Spang, C., Tran, D., and Koch, A. (2023). TaPaFuzz - An FPGA-Accelerated Framework for RISC-V IoT Graybox Fuzzing. In Workshop on Design and Architectures for Signal and Image Processing, DASIP ’23. Springer International Publishing.
Best Paper Award PreprintBibtex
@inproceedings{fm2023dasip, author = {Meisel, Florian and Volz, David and Spang, Christoph and Tran, Dat and Koch, Andreas}, title = {TaPaFuzz - An FPGA-Accelerated Framework for RISC-V IoT Graybox Fuzzing}, booktitle = {Workshop on Design and Architectures for Signal and Image Processing}, series = {DASIP '23}, year = {2023}, publisher = {Springer International Publishing} }
- Volz, D., Spang, C., and Koch, A. (2022). IPEC: Open-Source Design Automation for Inter-Processing Element Communication. In Applied Reconfigurable Computing. Architectures, Tools, and Applications. Springer International Publishing.
PreprintBibtex
@inproceedings{dv2022arc, author = {Volz, David and Spang, Christoph and Koch, Andreas}, title = {IPEC: Open-Source Design Automation for Inter-Processing Element Communication}, booktitle = {Applied Reconfigurable Computing. Architectures, Tools, and Applications}, year = {2022}, publisher = {Springer International Publishing} }
- Spang, C., Lavan, Y., Hartmann, M., Meisel, F., and Koch, A. (2022). DExIE - An IoT-Class Hardware Monitor for Real-Time Fine-Grained Control-Flow Integrity. In Journal of Signal Processing Systems (Vol. 94, pp. 739–752). doi: 10.1007/s11265-021-01732-5
Preprint DOI URLBibtex
@inproceedings{spang2022jsps, author = {Spang, Christoph and Lavan, Yannick and Hartmann, Marco and Meisel, Florian and Koch, Andreas}, title = {DExIE - An IoT-Class Hardware Monitor for Real-Time Fine-Grained Control-Flow Integrity}, journal = {Journal of Signal Processing Systems}, year = {2022}, month = jul, day = {01}, volume = {94}, number = {7}, pages = {739-752}, issn = {1939-8115}, doi = {10.1007/s11265-021-01732-5}, url = {https://doi.org/10.1007/s11265-021-01732-5} }
- Khan, B., Heinz, C., and Koch, A. (2022). DeLiBA: An Open-Source Hardware/Software Framework for the Development of Linux Block I/O Accelerators. In 2022 32nd International Conference on Field-Programmable Logic and Applications (FPL). doi: 10.1109/FPL57034.2022.00038
FPL Best Paper Award Preprint DOI SlidesBibtex
@inproceedings{khan2022fpl, title = {DeLiBA: An Open-Source Hardware/Software Framework for the Development of Linux Block I/O Accelerators}, author = {Khan, Babar and Heinz, Carsten and Koch, Andreas}, booktitle = {2022 32nd International Conference on Field-Programmable Logic and Applications (FPL)}, year = {2022}, doi = {10.1109/FPL57034.2022.00038} }
- Vinçon, T., Knödler, C., Solis-Vasquez, L., Bernhardt, A., Tamimi, S., Weber, L., Stock, F., et al. (2022). Near-Data Processing in Database Systems on Native Computational Storage under HTAP Workloads. In Proceedings of the VLDB Endowment, Volume 15. doi: 10.14778/3547305.3547307
Preprint DOI Slides VideoBibtex
@inproceedings{vincon2022vldb, author = {Vin\c{c}on, Tobias and Kn\"{o}dler, Christian and Solis-Vasquez, Leonardo and Bernhardt, Arthur and Tamimi, Sajjad and Weber, Lukas and Stock, Florian and Koch, Andreas and Petrov, Ilia}, title = {Near-Data Processing in Database Systems on Native Computational Storage under HTAP Workloads}, booktitle = {Proceedings of the VLDB Endowment, Volume 15}, year = {2022}, preprint = {https://dblab.reutlingen-university.de/paper/2022_VLDB_UpdateAwareNDP.pdf}, doi = {10.14778/3547305.3547307}, slides = {https://dblab.reutlingen-university.de/media/2022_VLDB_NDPunderHTAP.pdf}, video = {https://dblab.reutlingen-university.de/media/2022_VLDB_NDPunderHTAP.mp4} }
- Kalkhof, T., and Koch, A. (2022). Direct Device-to-Device Physical Page Migrations in Multi-FPGA Shared Virtual Memory Systems. In 2022 32nd International Conference on Field-Programmable Logic and Applications (FPL). doi: 10.1109/FPL57034.2022.00043
Preprint DOIBibtex
@inproceedings{kalkhof2022fpl, title = {Direct Device-to-Device Physical Page Migrations in Multi-FPGA Shared Virtual Memory Systems}, author = {Kalkhof, Torben and Koch, Andreas}, booktitle = {2022 32nd International Conference on Field-Programmable Logic and Applications (FPL)}, year = {2022}, doi = {10.1109/FPL57034.2022.00043} }
- Vinçon, T., Knödler, C., Bernhardt, A., Solis-Vasquez, L., Weber, L., Koch, A., and Petrov, I. (2022). Result-Set Management for NDP Operations on Smart Storage. In 18th International Workshop on Data Management on New Hardware (DaMoN). doi: 10.1145/3533737.3535097
Preprint DOI VideoBibtex
@inproceedings{vincon2022damon, author = {Vin\c{c}on, Tobias and Kn\"{o}dler, Christian and Bernhardt, Arthur and Solis-Vasquez, Leonardo and Weber, Lukas and Koch, Andreas and Petrov, Ilia}, title = {Result-Set Management for NDP Operations on Smart Storage}, booktitle = {18th International Workshop on Data Management on New Hardware (DaMoN)}, year = {2022}, doi = {10.1145/3533737.3535097}, preprint = {https://dblab.reutlingen-university.de/paper/2022_DAMON_NDPResultSetHandling_extended.pdf}, video = {https://dblab.reutlingen-university.de/paper/2022_DaMoN_resultsetMgmtRecording.mp4} }
- Tamimi, S., Stock, F., Bernhardt, A., Petrov, I., and Koch, A. (2022). An Evaluation of Using CCIX for Cache-Coherent Host-FPGA Interfacing. In 2022 IEEE 30th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).
HiPEAC Award Preprint SlidesBibtex
@inproceedings{tamimi2022fccm, author = {Tamimi, Sajjad and Stock, Florian and Bernhardt, Arthur and Petrov, Ilia and Koch, Andreas}, title = {An Evaluation of Using CCIX for Cache-Coherent Host-FPGA Interfacing}, booktitle = {2022 IEEE 30th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)}, year = {2022} }
- Damian, M., Oppermann, J., Spang, C., and Koch, A. (2022). SCAIE-V: An Open-Source SCAlable Interface for ISA Extensions for RISC-V Processors. In 2022 The 59th Design Automation Conference (DAC). doi: 10.1145/3489517.3530432
HiPEAC Award Preprint DOI URLBibtex
@inproceedings{damian2022dac, title = {SCAIE-V: An Open-Source SCAlable Interface for ISA Extensions for RISC-V Processors}, author = {Damian, Mihaela and Oppermann, Julian and Spang, Christoph and Koch, Andreas}, booktitle = {2022 The 59th Design Automation Conference (DAC)}, year = {2022}, url = {https://doi.org/10.1145/3489517.3530432}, doi = {10.1145/3489517.3530432} }
- Bernhardt, A., Tamimi, S., Vinçon, T., Knoedler, C., Stock, F., Heinz, C., Koch, A., et al. (2022). neoDBMS: In-situ Snapshots for Multi-Version DBMS on Native Computational Storage. In 2022 IEEE 38th International Conference on Data Engineering (ICDE).
PreprintBibtex
@inproceedings{tamimi2022icde, author = {Bernhardt, Arthur and Tamimi, Sajjad and Vin\c{c}on, Tobias and Knoedler, Christian and Stock, Florian and Heinz, Carsten and Koch, Andreas and Petrov, Ilia}, title = {neoDBMS: In-situ Snapshots for Multi-Version DBMS on Native Computational Storage}, booktitle = {2022 IEEE 38th International Conference on Data Engineering (ICDE)}, year = {2022} }
- Heinz, C., and Koch, A. (2022). On-Chip and Distributed Dynamic Parallelism for Task-based Hardware Accelerators. Journal of Signal Processing Systems. doi: 10.1007/s11265-022-01759-2
Preprint DOIBibtex
@article{heinz2022jsps, author = {Heinz, Carsten and Koch, Andreas}, title = {On-Chip and Distributed Dynamic Parallelism for Task-based Hardware Accelerators}, journal = {Journal of Signal Processing Systems}, year = {2022}, month = apr, day = {29}, issn = {1939-8115}, doi = {10.1007/s11265-022-01759-2}, preprint = {https://link.springer.com/content/pdf/10.1007/s11265-022-01759-2.pdf} }
- Bernhardt, A., Tamimi, S., Stock, F., Vinçon, T., Koch, A., and Petrov, I. (2022). Cache-Coherent Shared Locking for Transactionally Consistent Updates in Near-Data Processing DBMS on Smart Storage. In Proc. of the 25th International Conference on Extending Database Technology (EDBT).
Preprint Slides VideoBibtex
@inproceedings{tamimi2022edbt, author = {Bernhardt, Arthur and Tamimi, Sajjad and Stock, Florian and Vin\c{c}on, Tobias and Koch, Andreas and Petrov, Ilia}, title = {Cache-Coherent Shared Locking for Transactionally Consistent Updates in Near-Data Processing DBMS on Smart Storage}, booktitle = {Proc. of the 25th International Conference on Extending Database Technology (EDBT)}, year = {2022}, video = {https://www.youtube.com/embed/2gwnvKuzj_o} }
- Weber, L., Wirth, J., Sommer, L., and Koch, A. (2022). Exploiting High-Bandwidth Memory for FPGA- Acceleration of Inference on Sum-Product Networks. In 2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW).
PreprintBibtex
@inproceedings{weber2022raw, author = {Weber, Lukas and Wirth, Johannes and Sommer, Lukas and Koch, Andreas}, booktitle = {2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)}, title = {Exploiting High-Bandwidth Memory for FPGA- Acceleration of Inference on Sum-Product Networks}, year = {2022}, volume = {}, number = {} }
- Ecker, W., Adelt, P., Müller, W., Heckmann, R., Krstic, M., Herdt, V., Drechsler, R., et al. (2022). The Scale4Edge RISC-V Ecosystem. In 2022 Design, Automation & Test in Europe Conference (DATE). doi: 10.23919/DATE54114.2022.9774593
Preprint DOIBibtex
@inproceedings{s4e2022date, author = {Ecker, Wolfgang and Adelt, Peer and M{\"{u}}ller, Wolfgang and Heckmann, Reinhold and Krstic, Milos and Herdt, Vladimir and Drechsler, Rolf and Angst, Gerhard and Wimmer, Ralf and Mauderer, Andreas and Stahl, Rafael and Emrich, Karsten and Mueller{-}Gritschneder, Daniel and Becker, Bernd and Scholl, Philipp and Jentzsch, Eyck and Schlamelcher, Jan and Gr{\"{u}}ttner, Kim and Bernardo, Paul Palomero and Bringmann, Oliver and Damian, Mihaela and Oppermann, Julian and Koch, Andreas and Bormann, J{\"{o}}rg and Partzsch, Johannes and Mayr, Christian and Kunz, Wolfgang}, title = {The Scale4Edge {RISC-V} Ecosystem}, booktitle = {2022 Design, Automation {\&} Test in Europe Conference ({DATE})}, year = {2022}, doi = {10.23919/DATE54114.2022.9774593} }
- Oppermann, J., Reuter-Oppermann, M., Koch, A., and Sinnen, O. (2022). "Optimising" High-level Synthesis in CIRCT. In 2nd Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE’22).
Preprint VideoBibtex
@inproceedings{oppermann2022latte, title = {"Optimising" High-level Synthesis in CIRCT}, author = {Oppermann, Julian and Reuter-Oppermann, Melanie and Koch, Andreas and Sinnen, Oliver}, booktitle = {2nd Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE'22)}, year = {2022}, video = {https://youtu.be/7qMdPTLt12c} }
- Sommer, L., Axenie, C., and Koch, A. (2022). SPNC: An Open-Source MLIR-Based Compiler for Fast Sum-Product Network Inference on CPUs and GPUs. In 2022 IEEE/ACM International Symposium on Code Generation and Optimization (CGO).
PreprintBibtex
@inproceedings{sommer2022cgo, author = {Sommer, Lukas and Axenie, Cristian and Koch, Andreas}, booktitle = {2022 IEEE/ACM International Symposium on Code Generation and Optimization (CGO)}, title = {SPNC: An Open-Source MLIR-Based Compiler for Fast Sum-Product Network Inference on CPUs and GPUs}, year = {2022}, volume = {}, number = {} }
- Solis-Vasquez, L., Tillack, A. F., Santos-Martins, D., Koch, A., LeGrand, S., and Forli, S. (2021). Benchmarking the performance of irregular computations in AutoDock-GPU molecular docking. Parallel Computing. doi: 10.1016/j.parco.2021.102861
Preprint DOIBibtex
@article{solis2021parcosi, title = {Benchmarking the performance of irregular computations in AutoDock-GPU molecular docking}, author = {Solis-Vasquez, Leonardo and Tillack, Andreas F. and Santos-Martins, Diogo and Koch, Andreas and LeGrand, Scott and Forli, Stefano}, journal = {Parallel Computing}, year = {2021}, volume = {}, number = {}, pages = {}, doi = {10.1016/j.parco.2021.102861} }
- Kalkhof, T., and Koch, A. (2021). Efficient Physical Page Migrations in Shared Virtual Memory Reconfigurable Computing Systems. In 2021 International Conference on Field-Programmable Technology (ICFPT). doi: 10.1109/ICFPT52863.2021.9609831
Preprint DOIBibtex
@inproceedings{kalkhof2021fpt, title = {Efficient Physical Page Migrations in Shared Virtual Memory Reconfigurable Computing Systems}, author = {Kalkhof, Torben and Koch, Andreas}, booktitle = {2021 International Conference on Field-Programmable Technology (ICFPT)}, year = {2021}, doi = {10.1109/ICFPT52863.2021.9609831} }
- Heinz, C., and Koch, A. (2021). Near-Data FPGA-Accelerated Processing of Collective and Inference Operations in Disaggregated Memory Systems. In 2021 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC). doi: 10.1109/H2RC54759.2021.00010
Preprint DOIBibtex
@inproceedings{heinz2021h2rc, title = {Near-Data FPGA-Accelerated Processing of Collective and Inference Operations in Disaggregated Memory Systems}, author = {Heinz, Carsten and Koch, Andreas}, booktitle = {2021 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)}, year = {2021}, doi = {10.1109/H2RC54759.2021.00010} }
- Solis-Vasquez, L., Focht, E., and Koch, A. (2021). Mapping Irregular Computations for Molecular Docking to the SX-Aurora TSUBASA Vector Engine. In 11th Workshop on Irregular Applications: Architectures and Algorithms (IA3). doi: 10.1109/IA354616.2021.00008
Preprint DOI Slides MaterialBibtex
@inproceedings{solis2021ia3, title = {Mapping Irregular Computations for Molecular Docking to the SX-Aurora TSUBASA Vector Engine}, author = {Solis-Vasquez, Leonardo and Focht, Erich and Koch, Andreas}, booktitle = {11th Workshop on Irregular Applications: Architectures and Algorithms (IA3)}, year = {2021}, doi = {10.1109/IA354616.2021.00008}, material = {https://github.com/L30nardoSV/reproduce-ia3-2021-moldocking-vector} }
- Wirth, J., Hofmann, J. A., Thostrup, L., Binnig, C., and Koch, A. (2021). Scalable and Flexible High-Performance In-Network Processing of Hash Joins in Distributed Databases. In International Conference on Field-Programmable Technology (FPT).
PreprintBibtex
@inproceedings{wirth2021fpt, title = {Scalable and Flexible High-Performance In-Network Processing of Hash Joins in Distributed Databases}, author = {Wirth, Johannes and Hofmann, Jaco A. and Thostrup, Lasse and Binnig, Carsten and Koch, Andreas}, booktitle = {International Conference on Field-Programmable Technology (FPT)}, year = {2021} }
- Hartmann, M., Weber, L., Wirth, J., Sommer, L., and Koch, A. (2021). Optimizing a Hardware Network Stack to Realize an In-Network ML Inference Application. In 2021 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC).
Preprint SlidesBibtex
@inproceedings{hartmann2021h2rc, title = {Optimizing a Hardware Network Stack to Realize an In-Network ML Inference Application}, author = {Hartmann, Marco and Weber, Lukas and Wirth, Johannes and Sommer, Lukas and Koch, Andreas}, booktitle = {2021 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)}, year = {2021} }
- Solis-Vasquez, L., Focht, E., and Koch, A. (2021). Porting and Optimizing Molecular Docking onto the SX-Aurora TSUBASA Vector Computer. Supercomputing Frontiers and Innovations (JSFI), 8(2), 27–42. doi: 10.14529/jsfi210202
DOIBibtex
@article{solis2021jsfi, title = {Porting and Optimizing Molecular Docking onto the SX-Aurora TSUBASA Vector Computer}, author = {Solis-Vasquez, Leonardo and Focht, Erich and Koch, Andreas}, journal = {Supercomputing Frontiers and Innovations (JSFI)}, year = {2021}, volume = {8}, number = {2}, pages = {27-42}, doi = {10.14529/jsfi210202} }
- Sommer, L., Axenie, C., and Koch, A. (2021). SPNC: Fast Sum-Product Network Inference. In 2021 International Workshop on IoT, Edge, and Mobile for Embedded Machine Learning (ITEM).
PreprintBibtex
@inproceedings{sommer2021item, author = {Sommer, Lukas and Axenie, Cristian and Koch, Andreas}, booktitle = {2021 International Workshop on IoT, Edge, and Mobile for Embedded Machine Learning (ITEM)}, title = {SPNC: Fast Sum-Product Network Inference}, year = {2021}, volume = {}, number = {} }
- Weber, L., Sommer, L., Solis-Vasquez, L., Vinçon, T., Knödler, C., Bernhardt, A., Petrov, I., et al. (2021). A Framework for the Automatic Generation of FPGA-based Near-Data Processing Accelerators in Smart Storage Systems. In 2021 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) (pp. 136–143). doi: 10.1109/IPDPSW52791.2021.00028
Preprint DOI Slides VideoBibtex
@inproceedings{weber2021raw, author = {Weber, Lukas and Sommer, Lukas and Solis-Vasquez, Leonardo and Vinçon, Tobias and Knödler, Christian and Bernhardt, Arthur and Petrov, Ilia and Koch, Andreas}, booktitle = {2021 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)}, title = {A Framework for the Automatic Generation of FPGA-based Near-Data Processing Accelerators in Smart Storage Systems}, year = {2021}, volume = {}, number = {}, pages = {136-143}, doi = {10.1109/IPDPSW52791.2021.00028}, video = {https://www.youtube.com/watch?v=8d6DkVJVwc0&list=PLewc2qlpcOueI2cuqtHqopIcmmLCU0Cvn&index=10&ab_channel=NECSTLab} }
- Wirth, J., Hofmann, J. A., Thostrup, L., Koch, A., and Binnig, C. (2021). Exploiting 3D Memory for Accelerated In-Network Processing of Hash Joins in Distributed Databases. In S. Derrien, F. Hannig, P. C. Diniz, and D. Chillet (Eds.), Applied Reconfigurable Computing. Architectures, Tools, and Applications (pp. 18–32). Cham: Springer International Publishing.
PreprintBibtex
@inproceedings{10.1007/978-3-030-79025-7_2, author = {Wirth, Johannes and Hofmann, Jaco A. and Thostrup, Lasse and Koch, Andreas and Binnig, Carsten}, editor = {Derrien, Steven and Hannig, Frank and Diniz, Pedro C. and Chillet, Daniel}, title = {Exploiting 3D Memory for Accelerated In-Network Processing of Hash Joins in Distributed Databases}, booktitle = {Applied Reconfigurable Computing. Architectures, Tools, and Applications}, year = {2021}, publisher = {Springer International Publishing}, address = {Cham}, pages = {18--32}, isbn = {978-3-030-79025-7} }
- Heinz, C., and Koch, A. (2021). Supporting On-Chip Dynamic Parallelism for Task-Based Hardware Accelerators. In S. Derrien, F. Hannig, P. C. Diniz, and D. Chillet (Eds.), Applied Reconfigurable Computing. Architectures, Tools, and Applications (pp. 81–92). Cham: Springer International Publishing. doi: 10.1007/978-3-030-79025-7_6
Preprint DOIBibtex
@inproceedings{heinz2021arc, author = {Heinz, Carsten and Koch, Andreas}, editor = {Derrien, Steven and Hannig, Frank and Diniz, Pedro C. and Chillet, Daniel}, title = {Supporting On-Chip Dynamic Parallelism for Task-Based Hardware Accelerators}, booktitle = {Applied Reconfigurable Computing. Architectures, Tools, and Applications}, year = {2021}, publisher = {Springer International Publishing}, address = {Cham}, pages = {81--92}, isbn = {978-3-030-79025-7}, doi = {10.1007/978-3-030-79025-7_6} }
- Knödler, C., Vinçon, T., Bernhardt, A., Petrov, I., Solis-Vasquez, L., Weber, L., and Koch, A. (2021). A Cost Model for NDP-Aware Query Optimization for KV-Stores. In 17th International Workshop on Data Management on New Hardware (DaMoN). doi: 10.1145/3465998.3466013
Preprint DOIBibtex
@inproceedings{knoedler2021damon, title = {A Cost Model for NDP-Aware Query Optimization for KV-Stores}, author = {Kn\"{o}dler, Christian and Vin\c{c}on, Tobias and Bernhardt, Arthur and Petrov, Ilia and Solis-Vasquez, Leonardo and Weber, Lukas and Koch, Andreas}, booktitle = {17th International Workshop on Data Management on New Hardware (DaMoN)}, year = {2021}, doi = {10.1145/3465998.3466013} }
- Sommer, L., Halkenhäuser, M., Axenie, C., and Koch, A. (2021). SPNC: Accelerating Sum-Product Network Inference on CPUs and GPUs. In 2021 IEEE 32th International Conference on Application-specific Systems, Architectures and Processors (ASAP). IEEE.
PreprintBibtex
@inproceedings{sommer2021asap, title = {SPNC: Accelerating Sum-Product Network Inference on CPUs and GPUs}, author = {Sommer, Lukas and Halkenhäuser, Michael and Axenie, Cristian and Koch, Andreas}, booktitle = {2021 IEEE 32th International Conference on Application-specific Systems, Architectures and Processors (ASAP)}, year = {2021}, organization = {IEEE} }
- Spang, C., Meisel, F., and Koch, A. (2021). RT-LIFE: Portable RISC-V Interface for Real-Time Lightweight Security Enforcement. In Intl. Conf. on Embedded Computer Systems: Architectures, MOdeling and Simulation (SAMOS). Springer International Publishing.
Preprint SlidesBibtex
@inproceedings{spang2021samos, title = {RT-LIFE: Portable RISC-V Interface for Real-Time Lightweight Security Enforcement}, author = {Spang, Christoph and Meisel, Florian and Koch, Andreas}, booktitle = {Intl. Conf. on Embedded Computer Systems: Architectures, MOdeling and Simulation (SAMOS)}, year = {2021}, publisher = {Springer International Publishing} }
- Kruppe, H., Sommer, L., Weber, L., Oppermann, J., Axenie, C., and Koch, A. (2021). Efficient Operator Sharing Modulo Scheduling for Sum-Product Network Inference on FPGAs. In Intl. Conf. on Embedded Computer Systems: Architectures, MOdeling and Simulation (SAMOS). Springer International Publishing.
PreprintBibtex
@inproceedings{kruppe2021samos, title = {Efficient Operator Sharing Modulo Scheduling for Sum-Product Network Inference on FPGAs}, author = {Kruppe, Hanna and Sommer, Lukas and Weber, Lukas and Oppermann, Julian and Axenie, Cristian and Koch, Andreas}, booktitle = {Intl. Conf. on Embedded Computer Systems: Architectures, MOdeling and Simulation (SAMOS)}, year = {2021}, publisher = {Springer International Publishing} }
- Heinz, C., Hofmann, J., Korinth, J., Sommer, L., Weber, L., and Koch, A. (2021). The TaPaSCo Open-Source Toolflow. Journal of Signal Processing Systems. doi: 10.1007/s11265-021-01640-8
Preprint DOIBibtex
@article{heinz2021jsps, author = {Heinz, Carsten and Hofmann, Jaco and Korinth, Jens and Sommer, Lukas and Weber, Lukas and Koch, Andreas}, title = {The TaPaSCo Open-Source Toolflow}, journal = {Journal of Signal Processing Systems}, year = {2021}, month = may, day = {02}, issn = {1939-8115}, doi = {10.1007/s11265-021-01640-8}, preprint = {https://link.springer.com/content/pdf/10.1007/s11265-021-01640-8.pdf} }
- Wolf, D., Engel, A., Ruschke, T., Koch, A., and Hochberger, C. (2021). UltraSynth: Insights of a CGRA Integration into a Control
Engineering Environment. Journal of Signal Processing Systems, 1–17. doi: 10.1007/s11265-021-01641-7
Preprint DOIBibtex
@article{wolf2021jsps, author = {Wolf, Dennis and Engel, Andreas and Ruschke, Tajas and Koch, Andreas and Hochberger, Christian}, year = {2021}, month = feb, pages = {1-17}, title = {UltraSynth: Insights of a CGRA Integration into a Control Engineering Environment}, journal = {Journal of Signal Processing Systems}, doi = {10.1007/s11265-021-01641-7}, preprint = {https://doi.org/10.1007/s11265-021-01641-7} }
- Weber, L., Vincon, T., Knödler, C., Solis-Vasquez, L., Bernhardt, A., Petrov, I., and Koch, A. (2021). On the necessity of explicit cross-layer data formats in near-data processing systems. Distributed and Parallel Databases. doi: 10.1007/s10619-021-07328-z
DOIBibtex
@article{weber2021dapd, title = {On the necessity of explicit cross-layer data formats in near-data processing systems}, author = {Weber, Lukas and Vincon, Tobias and Knödler, Christian and Solis-Vasquez, Leonardo and Bernhardt, Arthur and Petrov, Ilia and Koch, Andreas}, journal = {Distributed and Parallel Databases}, year = {2021}, doi = {10.1007/s10619-021-07328-z} }
- Spang, C., Lavan, Y., Hartmann, M., Meisel, F., and Koch, A. (2021). DExIE - An IoT-Class Hardware Monitor for Real-Time Fine-Grained Control-Flow Integrity. In Workshop on Design and Architectures for Signal and Image Processing (14th Edition), DASIP ’21 (pp. 26–34). New York, NY, USA: Association for Computing Machinery. doi: 10.1145/3441110.3441146
Best Paper Award Preprint DOI URL SlidesBibtex
@inproceedings{spang2021dasip, author = {Spang, Christoph and Lavan, Yannick and Hartmann, Marco and Meisel, Florian and Koch, Andreas}, title = {DExIE - An IoT-Class Hardware Monitor for Real-Time Fine-Grained Control-Flow Integrity}, year = {2021}, isbn = {9781450389013}, publisher = {Association for Computing Machinery}, address = {New York, NY, USA}, url = {https://doi.org/10.1145/3441110.3441146}, doi = {10.1145/3441110.3441146}, booktitle = {Workshop on Design and Architectures for Signal and Image Processing (14th Edition)}, pages = {26–34}, numpages = {9}, keywords = {Fine-Grained Control Flow Integrity, IoT, Real Time, RISC-V, Hardware Security, Low Overhead}, location = {Budapest, Hungary}, series = {DASIP '21} }
- Santos-Martins, D., Solis-Vasquez, L., Tillack, A. F., Sanner, M. F., Koch, A., and Forli, S. (2021). Accelerating AutoDock4 with GPUs and Gradient-Based Local Search. Journal of Chemical Theory and Computation (JCTC). doi: 10.1021/acs.jctc.0c01006
Preprint DOIBibtex
@article{solis2020jctc, title = {Accelerating AutoDock4 with GPUs and Gradient-Based Local Search}, author = {Santos-Martins, Diogo and Solis-Vasquez, Leonardo and Tillack, Andreas F and Sanner, Michel F and Koch, Andreas and Forli, Stefano}, journal = {Journal of Chemical Theory and Computation (JCTC)}, year = {2021}, doi = {10.1021/acs.jctc.0c01006}, preprint = {https://chemrxiv.org/engage/chemrxiv/article-details/60c743f4702a9b2ad818a6f7} }
- Heinz, C., Hofmann, J. A., Sommer, L., and Koch, A. (2020). Improving Job Launch Rates in the TaPaSCo FPGA Middleware by Hardware/Software-Co-Design. In 2020 IEEE/ACM International Workshop on Runtime and Operating Systems for Supercomputers (ROSS) (pp. 22–30). doi: 10.1109/ROSS51935.2020.00008
Preprint DOIBibtex
@inproceedings{heinz2020ross, author = {{Heinz}, C. and {Hofmann}, J. A. and {Sommer}, L. and {Koch}, A.}, booktitle = {2020 IEEE/ACM International Workshop on Runtime and Operating Systems for Supercomputers (ROSS)}, title = {Improving Job Launch Rates in the TaPaSCo FPGA Middleware by Hardware/Software-Co-Design}, year = {2020}, volume = {}, number = {}, pages = {22-30}, doi = {10.1109/ROSS51935.2020.00008} }
- Solis-Vasquez, L., Santos-Martins, D., Tillack, A. F., Koch, A., Eberhardt, J., and Forli, S. (2020). Parallelizing Irregular Computations for Molecular Docking. In 10th Workshop on Irregular Applications: Architectures and Algorithms (IA3). doi: 10.1109/IA351965.2020.00008
Preprint DOI Slides MaterialBibtex
@inproceedings{solis2020ia3, author = {Solis-Vasquez, Leonardo and Santos-Martins, Diogo and Tillack, Andreas F. and Koch, Andreas and Eberhardt, J\'{e}r\^{o}me and Forli, Stefano}, title = {Parallelizing Irregular Computations for Molecular Docking}, booktitle = {10th Workshop on Irregular Applications: Architectures and Algorithms (IA3)}, year = {2020}, doi = {10.1109/IA351965.2020.00008}, material = {https://github.com/L30nardoSV/reproduce-ia3-moleculardocking} }
- Wolf, D. L., Spang, C., and Hochberger, C. (2020). Towards Purposeful Design Space Exploration of Heterogeneous CGRAs: Clock Frequency Estimation. In 2020 57th ACM/IEEE Design Automation Conference (DAC) (pp. 1–6). doi: 10.1109/DAC18072.2020.9218649
Preprint DOI SlidesBibtex
@inproceedings{spang2020dac, author = {{Wolf}, D. L. and {Spang}, C. and {Hochberger}, C.}, booktitle = {2020 57th ACM/IEEE Design Automation Conference (DAC)}, title = {Towards Purposeful Design Space Exploration of Heterogeneous CGRAs: Clock Frequency Estimation}, year = {2020}, volume = {}, number = {}, pages = {1-6}, doi = {10.1109/DAC18072.2020.9218649} }
- LeGrand, S., Scheinberg, A., Tillack, A. F., Thavappiragasam, M., Vermaas, J. V., Agarwal, R., Larkin, J., et al. (2020). GPU-Accelerated Drug Discovery with Docking on the Summit Supercomputer: Porting, Optimization, and Application to COVID-19 Research. In Proceedings of the 11th ACM International Conference on Bioinformatics, Computational Biology and Health Informatics (BCB). doi: 10.1145/3388440.3412472
Preprint DOIBibtex
@inproceedings{legrand2020bcb, author = {LeGrand, Scott and Scheinberg, Aaron and Tillack, Andreas F. and Thavappiragasam, Mathialakan and Vermaas, Josh V. and Agarwal, Rupesh and Larkin, Jeff and Poole, Duncan and Santos-Martins, Diogo and Solis-Vasquez, Leonardo and Koch, Andreas and Forli, Stefano and Hernandez, Oscar and Smith, Jeremy C. and Sedova, Ada}, title = {GPU-Accelerated Drug Discovery with Docking on the Summit Supercomputer: Porting, Optimization, and Application to COVID-19 Research}, booktitle = {Proceedings of the 11th ACM International Conference on Bioinformatics, Computational Biology and Health Informatics (BCB)}, year = {2020}, preprint = {https://arxiv.org/abs/2007.03678}, doi = {10.1145/3388440.3412472} }
- Glaser, M., Macfarlane, C., May, B., Fleck, S., Sommer, L., Stavesand, J.-E., Weber, C., et al. (2020). Open standards enable continuous softwaredevelopment in the automotive industry. AutoSens Brussels.
PreprintBibtex
@techreport{sommer2020autosens, author = {Glaser, Markus and Macfarlane, Charles and May, Benjamin and Fleck, Sven and Sommer, Lukas and Stavesand, Jann-Eve and Weber, Christian and Nguyen, Duong-Van and Ward, Enda and Rudkin, Ilya and Milz, Stefan and Oder, Rainer and Böhm, Frank and Schonlau, Benedikt and Hupfeld, Oliver and Koch, Andreas}, title = {Open standards enable continuous softwaredevelopment in the automotive industry}, institution = {AutoSens Brussels}, year = {2020} }
- Vinçon, T., Weber, L., Bernhardt, A., Riegger, C., Hardock, S., Knoedler, C., Stock, F., et al. (2020). nKV in Action: Accelerating KV-Stores on Native Computation Storage with Near-Data Processing. In Proceedings of the VLDB Endowment, Volume 13. doi: 10.14778/3415478.3415524
Preprint DOI Slides VideoBibtex
@inproceedings{weber2020vldb, author = {Vin\c{c}on, Tobias and Weber, Lukas and Bernhardt, Arthur and Riegger, Christian and Hardock, Sergey and Knoedler, Christian and Stock, Florian and Solis-Vasquez, Leonardo and Tamimi, Sajjad and Koch, Andreas}, title = {nKV in Action: Accelerating KV-Stores on Native Computation Storage with Near-Data Processing}, booktitle = {Proceedings of the VLDB Endowment, Volume 13}, year = {2020}, doi = {10.14778/3415478.3415524}, video = {https://www.youtube.com/watch?v=iiGh6Pj_A9k} }
- Huthmann, J., Podobas, A., Sommer, L., Koch, A., and Sano, K. (2020). Extending High-Level Synthesis with High-Performance Computing Performance Visualization. In 2020 IEEE International Conference on Cluster Computing (CLUSTER), CLUSTER ’20. Piscataway, NJ, USA: IEEE Press.
PreprintBibtex
@inproceedings{huthmann2020cluster, author = {Huthmann, Jens and Podobas, Artur and Sommer, Lukas and Koch, Andreas and Sano, Kentaro}, title = {Extending High-Level Synthesis with High-Performance Computing Performance Visualization}, booktitle = {2020 IEEE International Conference on Cluster Computing (CLUSTER)}, series = {CLUSTER '20}, year = {2020}, location = {Kobe, Japan}, publisher = {IEEE Press}, address = {Piscataway, NJ, USA} }
- Sommer, L., and Koch, A. (2020). OpenMP Device Offloading for Embedded Heterogeneous Platforms - Work-in-Progress. In Proceedings of the International Conference on Embedded Software, EMSOFT ’20. Piscataway, NJ, USA: IEEE Press.
PreprintBibtex
@inproceedings{sommer2020emsoft, author = {Sommer, Lukas and Koch, Andreas}, title = {OpenMP Device Offloading for Embedded Heterogeneous Platforms - Work-in-Progress}, booktitle = {Proceedings of the International Conference on Embedded Software}, series = {EMSOFT '20}, year = {2020}, location = {New York, NY, USA}, publisher = {IEEE Press}, address = {Piscataway, NJ, USA} }
- Huthmann, J., Sommer, L., Podobas, A., Koch, A., and Sano, K. (2020). OpenMP Device Offloading to FPGAs using the Nymble Infrastructure. In K. Miltfield, B. R. de Supinski, L. Koesterke, and J. Klinkenberg (Eds.), OpenMP: Portable Multi-level Parallelism on Modern Systems. Cham: Springer International Publishing.
PreprintBibtex
@inproceedings{huthmann2020iwomp, author = {Huthmann, Jens and Sommer, Lukas and Podobas, Artur and Koch, Andreas and Sano, Kentaro}, title = {OpenMP Device Offloading to FPGAs using the Nymble Infrastructure}, editor = {Miltfield, Kent and de Supinski, Bronis R. and Koesterke, Lars and Klinkenberg, Jannis}, booktitle = {OpenMP: Portable Multi-level Parallelism on Modern Systems}, year = {2020}, publisher = {Springer International Publishing}, address = {Cham} }
- Vinçon, T., Bernhardt, A., Petrov, I., Weber, L., and Koch, A. (2020). NKV: Near-Data Processing with KV-Stores on Native Computational Storage. In Proceedings of the 16th International Workshop on Data Management on New Hardware, DaMoN ’20. New York, NY, USA: Association for Computing Machinery. doi: 10.1145/3399666.3399934
Preprint DOI URL SlidesBibtex
@inproceedings{vincon2020damon, author = {Vin\c{c}on, Tobias and Bernhardt, Arthur and Petrov, Ilia and Weber, Lukas and Koch, Andreas}, title = {NKV: Near-Data Processing with KV-Stores on Native Computational Storage}, year = {2020}, isbn = {9781450380249}, publisher = {Association for Computing Machinery}, address = {New York, NY, USA}, url = {https://doi.org/10.1145/3399666.3399934}, doi = {10.1145/3399666.3399934}, booktitle = {Proceedings of the 16th International Workshop on Data Management on New Hardware}, articleno = {10}, numpages = {11}, location = {Portland, Oregon}, series = {DaMoN ’20} }
- Vinçon, T., Bernhardt, A., Weber, L., Koch, A., and Petrov, I. (2020). On the Necessity of Explicit Cross-Layer Data Formats in Near-Data Processing Systems. In 2020 IEEE 36th International Conference on Data Engineering Workshops (ICDEW) (pp. 109–114).
PreprintBibtex
@inproceedings{vincon2020hardbd, author = {{Vinçon}, T. and {Bernhardt}, A. and {Weber}, L. and {Koch}, A. and {Petrov}, I.}, booktitle = {2020 IEEE 36th International Conference on Data Engineering Workshops (ICDEW)}, title = {On the Necessity of Explicit Cross-Layer Data Formats in Near-Data Processing Systems}, year = {2020}, volume = {}, number = {}, pages = {109-114}, preprint = {http://db.ict.ac.cn/HardBD-Active-2020/papers/VinconBWKP-HardBDActive-2020.pdf} }
- Sommer, L., Stock, F., Solis-Vasquez, L., and Koch, A. (2020). DAPHNE - An Automotive Benchmark Suite for Parallel Programming Models on Embedded Heterogeneous Platforms. In D. Ziegenbein, S. Saidi, X. S. Hu, and S. Steinhorst (Eds.), Future Automotive HW/SW Platform Design (Dagstuhl Seminar 19502), Dagstuhl Reports (Vol. 9, pp. 28–66). Dagstuhl, Germany: Schloss Dagstuhl–Leibniz-Zentrum fuer Informatik. doi: 10.4230/DagRep.9.12.28
DOI URLBibtex
@inproceedings{sommer2020dagstuhl, author = {Sommer, Lukas and Stock, Florian and Solis-Vasquez, Leonardo and Koch, Andreas}, title = {DAPHNE - An Automotive Benchmark Suite for Parallel Programming Models on Embedded Heterogeneous Platforms}, booktitle = {{{Future Automotive HW/SW Platform Design (Dagstuhl Seminar 19502)}}}, year = {2020}, editor = {Ziegenbein, Dirk and Saidi, Selma and Hu, Xiaobo Sharon and Steinhorst, Sebastian}, volume = {9}, series = {Dagstuhl Reports}, pages = {28--66}, publisher = {{Schloss Dagstuhl--Leibniz-Zentrum fuer Informatik}}, address = {Dagstuhl, Germany}, url = {https://drops.dagstuhl.de/opus/volltexte/2020/12010}, urn = {urn:nbn:de:0030-drops-120101}, doi = {10.4230/DagRep.9.12.28}, annote = {Keywords: automotive, hw/sw platforms, real-time systems, systems design automation} }
- Sommer, L., Weber, L., Kumm, M., and Koch, A. (2020). Comparison of Arithmetic Number Formats for Inference in Sum-Product Networks on FPGAs. In 2020 IEEE 28th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) (pp. 1–10).
Best Paper Award, HiPEAC Award Preprint Slides VideoBibtex
@inproceedings{sommer2020fccm, author = {Sommer, Lukas and Weber, Lukas and Kumm, Martin and Koch, Andreas}, booktitle = {2020 IEEE 28th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)}, title = {Comparison of Arithmetic Number Formats for Inference in Sum-Product Networks on FPGAs}, year = {2020}, pages = {1-10}, video = {http://www.fccm.org/past/2020/forums/topic/comparison-of-arithmetic-number-formats-for-inference-in-sum-product-networks-on/} }
- Solis-Vasquez, L., Santos-Martins, D., Koch, A., and Forli, S. (2020). Evaluating the Energy Efficiency of OpenCL-accelerated AutoDock Molecular Docking. In 28th EUROMICRO International Conference on Parallel, Distributed and Network-Based Processing (PDP’20). doi: 10.1109/PDP50117.2020.00031
Preprint DOI SlidesBibtex
@inproceedings{solis2020pdp, author = {Solis-Vasquez, Leonardo and Santos-Martins, Diogo and Koch, Andreas and Forli, Stefano}, booktitle = {28th EUROMICRO International Conference on Parallel, Distributed and Network-Based Processing (PDP'20)}, title = {Evaluating the Energy Efficiency of OpenCL-accelerated AutoDock Molecular Docking}, year = {2020}, doi = {10.1109/PDP50117.2020.00031} }
- Sommer, L., Stock, F., Solis-Vasquez, L., and Koch, A. (2020). Using Parallel Programming Models for Automotive Workloads on Heterogeneous Systems - a Case Study. In 28th EUROMICRO International Conference on Parallel, Distributed and Network-Based Processing (PDP’20). doi: 10.1109/PDP50117.2020.00010
Preprint DOIBibtex
@inproceedings{sommer2020pdp, author = {Sommer, Lukas and Stock, Florian and Solis-Vasquez, Leonardo and Koch, Andreas}, booktitle = {28th EUROMICRO International Conference on Parallel, Distributed and Network-Based Processing (PDP'20)}, title = {Using Parallel Programming Models for Automotive Workloads on Heterogeneous Systems - a Case Study}, year = {2020}, doi = {10.1109/PDP50117.2020.00010}, keywords = {embedded, automotive, parallel programming, heterogeneous, OpenMP, OpenCL, CUDA} }
- Santos-Martins, D., Eberhardt, J., Bianco, G., Solis-Vasquez, L., Ambrosio, F. A., Koch, A., and Forli, S. (2019). D3R Grand Challenge 4: prospective pose prediction of BACE1 ligands with AutoDock-GPU. Journal of Computer-Aided Molecular Design. doi: 10.1007/s10822-019-00241-9
Preprint DOIBibtex
@article{santosmartins2019posepred, title = {D3R Grand Challenge 4: prospective pose prediction of BACE1 ligands with AutoDock-GPU}, author = {Santos-Martins, Diogo and Eberhardt, Jerome and Bianco, Giulia and Solis-Vasquez, Leonardo and Ambrosio, Francesca Alessandra and Koch, Andreas and Forli, Stefano}, journal = {Journal of Computer-Aided Molecular Design}, year = {2019}, preprint = {https://www.ncbi.nlm.nih.gov/pmc/articles/PMC7325737/pdf/nihms-1601909.pdf}, doi = {10.1007/s10822-019-00241-9} }
- El Khoury, L., Santos-Martins, D., Sasmal, S., Eberhardt, J., Bianco, G., Ambrosio, F. A., Solis-Vasquez, L., et al. (2019). Comparison of affinity ranking using AutoDock-GPU and MM-GBSA scores for BACE-1 inhibitors in the D3R Grand Challenge 4. Journal of Computer-Aided Molecular Design. doi: 10.1007/s10822-019-00240-w
Preprint DOIBibtex
@article{elkhoury2019affrank, title = {Comparison of affinity ranking using AutoDock-GPU and MM-GBSA scores for BACE-1 inhibitors in the D3R Grand Challenge 4}, author = {El Khoury, L{\'e}a and Santos-Martins, Diogo and Sasmal, Sukanya and Eberhardt, J{\'e}r{\^o}me and Bianco, Giulia and Ambrosio, Francesca Alessandra and Solis-Vasquez, Leonardo and Koch, Andreas and Forli, Stefano and Mobley, David L.}, journal = {Journal of Computer-Aided Molecular Design}, year = {2019}, preprint = {https://www.ncbi.nlm.nih.gov/pmc/articles/PMC7027993/pdf/nihms-1557830.pdf}, doi = {10.1007/s10822-019-00240-w} }
- Weber, L., Sommer, L., Oppermann, J., Molina, A., Kersting, K., and Koch, A. (2019). Resource-Efficient Logarithmic Number Scale Arithmetic for SPN Inference on FPGAs. In International Conference on Field-Programmable Technology (FPT).
Preprint Slides PosterBibtex
@inproceedings{weber2019relnsafsiof, title = {Resource-Efficient Logarithmic Number Scale Arithmetic for SPN Inference on FPGAs}, author = {Weber, Lukas and Sommer, Lukas and Oppermann, Julian and Molina, Alejandro and Kersting, Kristian and Koch, Andreas}, booktitle = {International Conference on Field-Programmable Technology (FPT)}, year = {2019} }
- Oppermann, J., Sommer, L., Weber, L., Reuter-Oppermann, M., Koch, A., and Sinnen, O. (2019). SkyCastle: A Resource-Aware Multi-Loop Scheduler for High-Level Synthesis. In International Conference on Field-Programmable Technology (FPT).
Preprint SlidesBibtex
@inproceedings{oppermann2019scamlsfhls, title = {SkyCastle: A Resource-Aware Multi-Loop Scheduler for High-Level Synthesis}, author = {Oppermann, Julian and Sommer, Lukas and Weber, Lukas and Reuter-Oppermann, Melanie and Koch, Andreas and Sinnen, Oliver}, booktitle = {International Conference on Field-Programmable Technology (FPT)}, year = {2019} }
- Krude, J., Hofmann, J., Eichholz, M., Wehrle, K., Koch, A., and Mezini, M. (2019). Online Reprogrammable Multi Tenant Switches. In 1st ACM CoNEXT Workshop on Emerging in-Network Computing Paradigms (CoNEXT ENCP’19). ACM.
PreprintBibtex
@inproceedings{krude2019ormts, title = {Online Reprogrammable Multi Tenant Switches}, author = {Krude, Johannes and Hofmann, Jaco and Eichholz, Matthias and Wehrle, Klaus and Koch, Andreas and Mezini, Mira}, booktitle = {1st ACM CoNEXT Workshop on Emerging in-Network Computing Paradigms (CoNEXT ENCP'19)}, year = {2019}, organization = {ACM} }
- Heinz, C., Lavan, Y., Hofmann, J., and Koch, A. (2019). A Catalog and In-Hardware Evaluation of Open-Source Drop-In Compatible RISC-V Softcore Processors. In IEEE Proc. International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE. doi: 10.1109/ReConFig48160.2019.8994796
Preprint DOIBibtex
@inproceedings{heinz2019reconfig, title = {A Catalog and In-Hardware Evaluation of Open-Source Drop-In Compatible RISC-V Softcore Processors}, author = {Heinz, Carsten and Lavan, Yannick and Hofmann, Jaco and Koch, Andreas}, booktitle = {IEEE Proc. International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, year = {2019}, organization = {IEEE}, doi = {10.1109/ReConFig48160.2019.8994796} }
- Ober, M., Hofmann, J., Sommer, L., Weber, L., and Koch, A. (2019). High-Throughput Multi-Threaded Sum-Product Network Inference in the Reconfigurable Cloud. In Fifth International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC).
PreprintBibtex
@inproceedings{ober2019h2rc, title = {High-Throughput Multi-Threaded Sum-Product Network Inference in the Reconfigurable Cloud}, author = {Ober, Micha and Hofmann, Jaco and Sommer, Lukas and Weber, Lukas and Koch, Andreas}, booktitle = {Fifth International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)}, year = {2019} }
- Hofmann, J., Thostrup, L., Ziegler, T., Binnig, C., and Koch, A. (2019). High-Performance In-Network Data Processing. In International Workshop on Accelerating Analytics and Data Management
Systems Using Modern Processor and Storage Architectures, ADMS@VLDB
2019, Los Angeles, United States.
PreprintBibtex
@inproceedings{adms2019, author = {Hofmann, Jaco and Thostrup, Lasse and Ziegler, Tobias and Binnig, Carsten and Koch, Andreas}, title = {High-Performance In-Network Data Processing}, booktitle = {International Workshop on Accelerating Analytics and Data Management Systems Using Modern Processor and Storage Architectures, ADMS@VLDB 2019, Los Angeles, United States.}, year = {2019} }
- Sommer, L., Stock, F., Solis-Vasquez, L., and Koch, A. (2019). Work-in-Progress: DAPHNE - Automotive Benchmark Suite for Parallel Programming Models on Embedded Heterogeneous Platforms. In Proceedings of the International Conference on Embedded Software (accepted for publication 07/2019), EMSOFT ’19. Piscataway, NJ, USA: IEEE Press. doi: 10.1145/3349568.3351547
Preprint DOIBibtex
@inproceedings{emsoft2019, author = {Sommer, Lukas and Stock, Florian and Solis-Vasquez, Leonardo and Koch, Andreas}, title = {Work-in-Progress: DAPHNE - Automotive Benchmark Suite for Parallel Programming Models on Embedded Heterogeneous Platforms}, booktitle = {Proceedings of the International Conference on Embedded Software (accepted for publication 07/2019)}, series = {EMSOFT '19}, year = {2019}, location = {New York, NY, USA}, publisher = {IEEE Press}, address = {Piscataway, NJ, USA}, doi = {10.1145/3349568.3351547} }
- Sommer, L., Stock, F., Solis-Vasquez, L., and Koch, A. (2019). EPHoS: Evaluation of Programming - Models for Heterogeneous Systems. FAT-Schriftenreihe 317. Forschungsvereinigung Automobiltechik. Retrieved from https://www.vda.de/de/services/Publikationen/fat-schriftenreihe-317.html
URLBibtex
@article{fat317, title = {EPHoS: Evaluation of Programming - Models for Heterogeneous Systems}, author = {Sommer, Lukas and Stock, Florian and Solis-Vasquez, Leonardo and Koch, Andreas}, booktitle = {FAT-Schriftenreihe 317}, year = {2019}, publisher = {Forschungsvereinigung Automobiltechik}, url = {https://www.vda.de/de/services/Publikationen/fat-schriftenreihe-317.html} }
- Wolf, D., Ruschke, T., Hochberger, C., Engel, A., and Koch, A. (2019). UltraSynth: Integration of a CGRA into a Control Engineering Environment. In C. Hochberger, B. Nelson, A. Koch, R. Woods, and P. Diniz (Eds.), Applied Reconfigurable Computing (pp. 247–261). Cham: Springer International Publishing.
PreprintBibtex
@inproceedings{engel2019ultrasynth, author = {Wolf, Dennis and Ruschke, Tajas and Hochberger, Christian and Engel, Andreas and Koch, Andreas}, editor = {Hochberger, Christian and Nelson, Brent and Koch, Andreas and Woods, Roger and Diniz, Pedro}, title = {UltraSynth: Integration of a CGRA into a Control Engineering Environment}, booktitle = {Applied Reconfigurable Computing}, year = {2019}, publisher = {Springer International Publishing}, address = {Cham}, pages = {247--261}, isbn = {978-3-030-17227-5}, preprint = {https://link.springer.com/chapter/10.1007/978-3-030-17227-5_18} }
- Korinth, J., Hofmann, J., Heinz, C., and Koch, A. (2019). The TaPaSCo Open-Source Toolflow for the Automated Composition of Task-Based Parallel Reconfigurable Computing Systems. In International Symposium on Applied Reconfigurable Computing (ARC). doi: 10.1007/978-3-030-17227-5_16
Preprint DOIBibtex
@inproceedings{korinth2019ttpscostactbprcs, title = {The TaPaSCo Open-Source Toolflow for the Automated Composition of Task-Based Parallel Reconfigurable Computing Systems}, author = {Korinth, Jens and Hofmann, Jaco and Heinz, Carsten and Koch, Andreas}, booktitle = {International Symposium on Applied Reconfigurable Computing (ARC)}, year = {2019}, doi = {10.1007/978-3-030-17227-5_16} }
- Oppermann, J., Sittel, P., Kumm, M., Reuter-Oppermann, M., Koch, A., and Sinnen, O. (2019). Design-Space Exploration with Multi-Objective Resource-Aware Modulo Scheduling. In International European Conference on Parallel and Distributed Computing (Euro-Par), Göttingen, Germany.
Preprint SlidesBibtex
@inproceedings{oppermann2019dsemorams, author = {Oppermann, Julian and Sittel, Patrick and Kumm, Martin and Reuter{-}Oppermann, Melanie and Koch, Andreas and Sinnen, Oliver}, title = {{Design-Space Exploration with Multi-Objective Resource-Aware Modulo Scheduling}}, booktitle = {International European Conference on Parallel and Distributed Computing (Euro-Par), Göttingen, Germany}, year = {2019} }
- Oppermann, J., Reuter-Oppermann, M., Sommer, L., Koch, A., and Sinnen, O. (2019). Exact and Practical Modulo Scheduling for High-Level Synthesis. TRETS, 12(2), 8:1–8:26. doi: 10.1145/3317670
Preprint DOIBibtex
@article{oppermann2019epmshs, author = {Oppermann, Julian and Reuter{-}Oppermann, Melanie and Sommer, Lukas and Koch, Andreas and Sinnen, Oliver}, title = {Exact and Practical Modulo Scheduling for High-Level Synthesis}, journal = {{TRETS}}, volume = {12}, number = {2}, pages = {8:1--8:26}, year = {2019}, doi = {10.1145/3317670} }
- Kruppe, R., Oppermann, J., Sommer, L., and Koch, A. (2019). Extending LLVM for Lightweight SPMD Vectorization: Using SIMD and Vector Instructions Easily from Any Language . In 2019 International Symposium on Code Generation and Optimization.
PreprintBibtex
@inproceedings{kruppe2019ellvmlspmdvusimdvieal, title = {Extending LLVM for Lightweight SPMD Vectorization: Using SIMD and Vector Instructions Easily from Any Language }, author = {Kruppe, Robin and Oppermann, Julian and Sommer, Lukas and Koch, Andreas}, booktitle = {2019 International Symposium on Code Generation and Optimization}, year = {2019} }
- Oppermann, J., Sommer, L., and Koch, A. (2019). SpExSim: assessing kernel suitability for C-based high-level hardware synthesis. In Journal of Supercomputing.
Preprint The original publication is available at www.springerlink.comBibtex
@inproceedings{oppermann2019sesc, title = {SpExSim: assessing kernel suitability for C-based high-level hardware synthesis}, author = {Oppermann, Julian and Sommer, Lukas and Koch, Andreas}, booktitle = {Journal of Supercomputing}, year = {2019}, springer = {http://link.springer.com/article/10.1007/s11227-017-2101-z} }
- Sommer, L., Oppermann, J., Molina, A., Binnig, C., Kersting, K., and Koch, A. (2018). Automatic Mapping of the Sum-Product Network Inference Problem to FPGA-based Accelerators. In IEEE International Conference on Computer Design (ICCD). IEEE.
PreprintBibtex
@inproceedings{sommer2018amspnipfpgaa, title = {Automatic Mapping of the Sum-Product Network Inference Problem to FPGA-based Accelerators}, author = {Sommer, Lukas and Oppermann, Julian and Molina, Alejandro and Binnig, Carsten and Kersting, Kristian and Koch, Andreas}, booktitle = {IEEE International Conference on Computer Design (ICCD)}, year = {2018}, organization = {IEEE} }
- Solis-Vasquez, L., and Koch, A. (2018). A Case Study in Using OpenCL on FPGAs: Creating an Open-Source Accelerator of the AutoDock Molecular Docking Software. In Fifth International Workshop on FPGAs for Software Programmers (FSP). Retrieved from https://ieeexplore.ieee.org/document/8470463
Preprint URL Slides MaterialBibtex
@inproceedings{solis-vasquez2018acsuoclfpgacosaadmds, title = {A Case Study in Using OpenCL on FPGAs: Creating an Open-Source Accelerator of the AutoDock Molecular Docking Software}, author = {Solis-Vasquez, Leonardo and Koch, Andreas}, booktitle = {Fifth International Workshop on FPGAs for Software Programmers (FSP)}, year = {2018}, url = {https://ieeexplore.ieee.org/document/8470463}, material = {https://git.esa.informatik.tu-darmstadt.de/docking/ocladock-fpga} }
- Oppermann, J., Vollbrecht, S., Reuter-Oppermann, M., Sinnen, O., and Koch, A. (2018). Work in Progress: GeMS: A Generator for Modulo Scheduling Problems. In Intl. Conf. on Compilers, Architectures and Synthesis For Embedded Systems (CASES).
Preprint Slides PosterBibtex
@inproceedings{oppermann2018wpgmsagmsp, title = {Work in Progress: GeMS: A Generator for Modulo Scheduling Problems}, author = {Oppermann, Julian and Vollbrecht, Sebastian and Reuter-Oppermann, Melanie and Sinnen, Oliver and Koch, Andreas}, booktitle = {Intl. Conf. on Compilers, Architectures and Synthesis For Embedded Systems (CASES)}, year = {2018} }
- Oppermann, J., Reuter-Oppermann, M., Sommer, L., Sinnen, O., and Koch, A. (2018). Dependence Graph Preprocessing for Faster Exact Modulo Scheduling in High-level Synthesis. In Intl. Conf. on Field Programmable Logic and Applications (FPL).
Preprint SlidesBibtex
@inproceedings{oppermann2018dgpfemshs, title = {Dependence Graph Preprocessing for Faster Exact Modulo Scheduling in High-level Synthesis}, author = {Oppermann, Julian and Reuter-Oppermann, Melanie and Sommer, Lukas and Sinnen, Oliver and Koch, Andreas}, booktitle = {Intl. Conf. on Field Programmable Logic and Applications (FPL)}, year = {2018} }
- Sittel, P., Kumm, M., Oppermann, J., Möller, K., Zipf, P., and Koch, A. (2018). ILP-based Modulo Scheduling and Binding for Register Minimization. In Intl. Conf. on Field Programmable Logic and Applications (FPL).
PreprintBibtex
@inproceedings{sittel2018ilpmsbrm, title = {ILP-based Modulo Scheduling and Binding for Register Minimization}, author = {Sittel, Patrick and Kumm, Martin and Oppermann, Julian and Möller, Konrad and Zipf, Peter and Koch, Andreas}, booktitle = {Intl. Conf. on Field Programmable Logic and Applications (FPL)}, year = {2018} }
- Sittel, P., Oppermann, J., Kumm, M., Koch, A., and Zipf, P. (2018). HatScheT: A Contribution to Agile HLS. In FPGAs for Software Programmers (FSP).
PreprintBibtex
@inproceedings{sittel2018hstacahls, title = {HatScheT: A Contribution to Agile HLS}, author = {Sittel, Patrick and Oppermann, Julian and Kumm, Martin and Koch, Andreas and Zipf, Peter}, booktitle = {FPGAs for Software Programmers (FSP)}, year = {2018} }
- Sommer, L., Oppermann, J., Molina, A., Binnig, C., Kersting, K., and Koch, A. (2018). Automatic Synthesis of FPGA-based Accelerators for the Sum-Product Network Inference Problem. In ICML 2018 Workshop on Tractable Probabilistic Models (TPM). ICML.
PreprintBibtex
@inproceedings{sommer2018asfpgaaspnip, title = {Automatic Synthesis of FPGA-based Accelerators for the Sum-Product Network Inference Problem}, author = {Sommer, Lukas and Oppermann, Julian and Molina, Alejandro and Binnig, Carsten and Kersting, Kristian and Koch, Andreas}, booktitle = {ICML 2018 Workshop on Tractable Probabilistic Models (TPM)}, year = {2018}, organization = {ICML} }
- Kruppe, R., Oppermann, J., and Koch, A. (2018). Supporting the RISC-V Vector Extensions in LLVM. In 2018 European LLVM Developers Meeting.
Slides Video MaterialBibtex
@inproceedings{kruppe2018sriscvvellvm, title = {Supporting the RISC-V Vector Extensions in LLVM}, author = {Kruppe, Robin and Oppermann, Julian and Koch, Andreas}, booktitle = {2018 European LLVM Developers Meeting}, year = {2018}, video = {https://youtu.be/iSMLYHRlNVc}, slides = {http://llvm.org/devmtg/2018-04/slides/Kruppe-Supporting%20the%20Risc-V%20vector%20ext.pdf}, material = {https://llvm.org/devmtg/2018-04/talks.html#Lightning_18} }
- Sommer, L., Oppermann, J., Korinth, J., and Koch, A. (2018). Offloading OpenMP Target Regions to FPGA Accelerators Using LLVM. In 2018 European LLVM Developers Meeting.
PreprintBibtex
@inproceedings{sommer2018oomptrfpgaaullvm, title = {Offloading OpenMP Target Regions to FPGA Accelerators Using LLVM}, author = {Sommer, Lukas and Oppermann, Julian and Korinth, Jens and Koch, Andreas}, booktitle = {2018 European LLVM Developers Meeting}, year = {2018} }
- Vincon, T., Haddock, S., Riegger, C., Oppermann, J., Koch, A., and Petrov, I. (2018). NoFTL-KV: Tackling Write-Amplification on KV-Stores with Native Storage Management. In Proc. of the 21st International Conference on Extending Database Technology (EDBT).
PreprintBibtex
@inproceedings{vincon2018nftlkvtwakvsnsm, title = {NoFTL-KV: Tackling Write-Amplification on KV-Stores with Native Storage Management}, author = {Vincon, Tobias and Haddock, Sergey and Riegger, Christian and Oppermann, Julian and Koch, Andreas and Petrov, Ilia}, booktitle = {Proc. of the 21st International Conference on Extending Database Technology (EDBT)}, year = {2018} }
- Liebig, B., Oppermann, J., Sinnen, O., and Koch, A. (2018). Improved High-Level Synthesis for Complex CellML Models. In Proc. 14th International Symposium on Applied Reconfigurable Computing (ARC).
PreprintBibtex
@inproceedings{liebig2018ihlsccmlm, title = {Improved High-Level Synthesis for Complex CellML Models}, author = {Liebig, Björn and Oppermann, Julian and Sinnen, Oliver and Koch, Andreas}, booktitle = {Proc. 14th International Symposium on Applied Reconfigurable Computing (ARC)}, year = {2018} }
- Engel, A., and Koch, A. (2017). Energy-Efficient Reconfiguration of Flash-based FPGAs in Heterogeneous Wireless Sensor Nodes. In IEEE Proc. International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE.
PreprintBibtex
@inproceedings{engel2017eerffpgahwsn, title = {Energy-Efficient Reconfiguration of Flash-based FPGAs in Heterogeneous Wireless Sensor Nodes}, author = {Engel, Andreas and Koch, Andreas}, booktitle = {IEEE Proc. International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, year = {2017}, organization = {IEEE} }
- Sommer, L., Oppermann, J., Hofmann, J., and Koch, A. (2017). Synthesis of Interleaved Multithreaded Accelerators from OpenMP Loops. In 2017 International Conference on Reconfigurable Computing and FPGAs (ReConFig’17). IEEE.
PreprintBibtex
@inproceedings{sommer2017simaompl, title = {Synthesis of Interleaved Multithreaded Accelerators from OpenMP Loops}, author = {Sommer, Lukas and Oppermann, Julian and Hofmann, Jaco and Koch, Andreas}, booktitle = {2017 International Conference on Reconfigurable Computing and FPGAs (ReConFig'17)}, year = {2017}, organization = {IEEE} }
- Sommer, L., Korinth, J., and Koch, A. (2017). OpenMP Device Offloading to FPGA Accelerators. In International Conference on Application-specific Systems, Architectures and Processors (ASAP).
Preprint PosterBibtex
@inproceedings{sommer2017ompdofpgaa, title = {OpenMP Device Offloading to FPGA Accelerators}, author = {Sommer, Lukas and Korinth, Jens and Koch, Andreas}, booktitle = {International Conference on Application-specific Systems, Architectures and Processors (ASAP)}, year = {2017} }
- Solis-Vasquez, L., and Koch, A. (2017). A Performance and Energy Evaluation of OpenCL-accelerated Molecular Docking. In Fifth International Workshop on OpenCL (IWOCL). doi: 10.1145/3078155.3078167
Preprint DOI Slides MaterialBibtex
@inproceedings{solis-vasquez2017apeeoclmd, title = {A Performance and Energy Evaluation of OpenCL-accelerated Molecular Docking}, author = {Solis-Vasquez, Leonardo and Koch, Andreas}, booktitle = {Fifth International Workshop on OpenCL (IWOCL)}, year = {2017}, doi = {10.1145/3078155.3078167}, material = {https://git.esa.informatik.tu-darmstadt.de/docking/ocladock} }
- Liebig, B., and Koch, A. (2016). High-Level Synthesis of Resource-Shared Microarchitectures from Irregular Complex C-Code. In International Conference on Field-Programmable Technology (FPT).
PreprintBibtex
@inproceedings{liebig2016hlsrsmiccc, title = {High-Level Synthesis of Resource-Shared Microarchitectures from Irregular Complex C-Code}, author = {Liebig, Björn and Koch, Andreas}, booktitle = {International Conference on Field-Programmable Technology (FPT)}, year = {2016} }
- Hofmann, J., Korinth, J., and Koch, A. (2016). A Scalable Latency-Insensitive Architecture for FPGA-Accelerated Semi-Global Matching in Stereo Vision Applications. In IEEE Proc. International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE.
PreprintBibtex
@inproceedings{hofmann2016asliafpgaasgmsva, title = {A Scalable Latency-Insensitive Architecture for FPGA-Accelerated Semi-Global Matching in Stereo Vision Applications}, author = {Hofmann, Jaco and Korinth, Jens and Koch, Andreas}, booktitle = {IEEE Proc. International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, year = {2016}, organization = {IEEE} }
- Engel, A., and Koch, A. (2016). Heterogeneous Wireless Sensor Nodes That Target the Internet of Things. In IEEE Micro Magazine. IEEE.
PreprintBibtex
@inproceedings{engel2016hwsnttit, title = {Heterogeneous Wireless Sensor Nodes That Target the Internet of Things}, author = {Engel, Andreas and Koch, Andreas}, booktitle = {IEEE Micro Magazine}, year = {2016}, organization = {IEEE} }
- Sommer, L., Oppermann, J., and Koch, A. (2016). C-based Synthesis of Area-Efficient Accelerators for OpenMP Worksharing Loops. In Second International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC).
PreprintBibtex
@inproceedings{sommer2016csaeaompwl, title = {C-based Synthesis of Area-Efficient Accelerators for OpenMP Worksharing Loops}, author = {Sommer, Lukas and Oppermann, Julian and Koch, Andreas}, booktitle = {Second International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)}, year = {2016} }
- Oppermann, J., Koch, A., Reuter-Oppermann, M., and Sinnen, O. (2016). ILP-based Modulo Scheduling for High-level Synthesis. In International Conference on Compilers, Architectures and Synthesis For Embedded Systems (CASES).
Preprint Slides Poster MaterialBibtex
@inproceedings{oppermann2016ilpmshs, title = {ILP-based Modulo Scheduling for High-level Synthesis}, author = {Oppermann, Julian and Koch, Andreas and Reuter-Oppermann, Melanie and Sinnen, Oliver}, booktitle = {International Conference on Compilers, Architectures and Synthesis For Embedded Systems (CASES)}, year = {2016}, material = {http://dx.doi.org/10.1145/2968455.2968512} }
- Brugnoni, S., Corbat, T., Sommerlad, P., Suter, T., Korinth, J., Chevallerie, D. de la, and Koch, A. (2016). Automated Generation of Reconfigurable Systems-on-Chip by Interactive Code Transformations for High-Level Synthesis. In Third International Workshop on FPGAs Software Programmers (FSP).
PreprintBibtex
@inproceedings{brugnoni2016agrscicthls, title = {Automated Generation of Reconfigurable Systems-on-Chip by Interactive Code Transformations for High-Level Synthesis}, author = {Brugnoni, Silvano and Corbat, Thomas and Sommerlad, Peter and Suter, Toni and Korinth, Jens and de la Chevallerie, David and Koch, Andreas}, booktitle = {Third International Workshop on FPGAs Software Programmers (FSP)}, year = {2016} }
- Hochberger, C., Koch, A., and Weinhardt, M. (2016). Third International Workshop on FPGAs for Software Programmers (FSP 2016). In Proceedings Volume.
Bibtex
@inproceedings{hochberger2016tiwfpgaspfsp, title = {Third International Workshop on FPGAs for Software Programmers (FSP 2016)}, author = {Hochberger, Christian and Koch, Andreas and Weinhardt, Markus}, booktitle = {Proceedings Volume}, year = {2016} }
- Oppermann, J., and Koch, A. (2016). Detecting Kernels Suitable for C-based High-Level Hardware Synthesis. In 2nd International Workshop on Reengineering for Parallelism in Heterogeneous Parallel Platforms (RePara).
PreprintBibtex
@inproceedings{oppermann2016dkschlhs, title = {Detecting Kernels Suitable for C-based High-Level Hardware Synthesis}, author = {Oppermann, Julian and Koch, Andreas}, booktitle = {2nd International Workshop on Reengineering for Parallelism in Heterogeneous Parallel Platforms (RePara)}, year = {2016} }
- Hofmann, J., Korinth, J., and Koch, A. (2016). A Scalable High-Performance Hardware Architecture for Real-Time Stereo Vision by Semi-Global Matching. In IEEE Conference on Computer Vision and Pattern Recognition (CVPR) Workshops. IEEE.
Best-Paper Runner-Up PreprintBibtex
@inproceedings{hofmann2016ashphartsvsgm, title = {A Scalable High-Performance Hardware Architecture for Real-Time Stereo Vision by Semi-Global Matching}, author = {Hofmann, Jaco and Korinth, Jens and Koch, Andreas}, booktitle = {IEEE Conference on Computer Vision and Pattern Recognition (CVPR) Workshops}, year = {2016}, organization = {IEEE} }
- Huthmann, J., and Koch, A. (2015). Optimized High-Level Synthesis of SMT Multi-Threaded Hardware Accelerators. In International Conference on Field-Programmable Technology (FPT).
PreprintBibtex
@inproceedings{huthmann2015ohlssmtmtha, title = {Optimized High-Level Synthesis of SMT Multi-Threaded Hardware Accelerators}, author = {Huthmann, Jens and Koch, Andreas}, booktitle = {International Conference on Field-Programmable Technology (FPT)}, year = {2015} }
- Korinth, J., Chevallerie, D. de la, and Koch, A. (2015). ThreadPoolComposer – An Open-Source FPGA Toolchain for Software Developers. In Second International Workshop on FPGAs Software Programmers (FSP).
PreprintBibtex
@inproceedings{korinth2015tpcaosfpgatsd, title = {ThreadPoolComposer – An Open-Source FPGA Toolchain for Software Developers}, author = {Korinth, Jens and de la Chevallerie, David and Koch, Andreas}, booktitle = {Second International Workshop on FPGAs Software Programmers (FSP)}, year = {2015} }
- Korinth, J., Chevallerie, D. de la, and Koch, A. (2015). An Open-Source Tool Flow for the Composition of Reconfigurable Hardware Thread Pool Architectures. In The 23rd IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE.
PreprintBibtex
@inproceedings{korinth2015aostfcrhtpa, title = {An Open-Source Tool Flow for the Composition of Reconfigurable Hardware Thread Pool Architectures}, author = {Korinth, Jens and de la Chevallerie, David and Koch, Andreas}, booktitle = {The 23rd IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM)}, year = {2015}, organization = {IEEE} }
- Chevallerie, D. de la, Korinth, J., and Koch, A. (2015). ffLink: A Lightweight High-Performance Open-Source PCI Express Gen3 Interface for Reconfigurable Accelerators. In ACM SIGARCH Computer Architecture News. ACM.
PreprintBibtex
@inproceedings{de2015lalhpospciegira, title = {ffLink: A Lightweight High-Performance Open-Source PCI Express Gen3 Interface for Reconfigurable Accelerators}, author = {de la Chevallerie, David and Korinth, Jens and Koch, Andreas}, booktitle = {ACM SIGARCH Computer Architecture News}, year = {2015}, organization = {ACM} }
- Engel, A., and Koch, A. (2015). Accelerated Clock Drift Estimation for High-Precision Wireless Time-Synchronization. In IEEE Proc. Conference on Local Computer Networks (LCN). IEEE.
PreprintBibtex
@inproceedings{engel2015acdehpwts, title = {Accelerated Clock Drift Estimation for High-Precision Wireless Time-Synchronization}, author = {Engel, Andreas and Koch, Andreas}, booktitle = {IEEE Proc. Conference on Local Computer Networks (LCN)}, year = {2015}, organization = {IEEE} }
- Engel, A., and Koch, A. (2015). DEMO: The Need for Wireless Clock Drift Estimation and Its Acceleration on a Heterogeneous Sensor Node. In IEEE Proc. Conference on Local Computer Networks (LCN). IEEE.
PreprintBibtex
@inproceedings{engel2015demotnwcdeiahsn, title = {DEMO: The Need for Wireless Clock Drift Estimation and Its Acceleration on a Heterogeneous Sensor Node}, author = {Engel, Andreas and Koch, Andreas}, booktitle = {IEEE Proc. Conference on Local Computer Networks (LCN)}, year = {2015}, organization = {IEEE} }
- Engel, A., Siebel, T., and Koch, A. (2015). A Heterogeneous System Architecture for Low-Power Wireless Sensor Nodes in Compute-intensive Distributed Applications. In IEEE Proc. Conference on Local Computer Networks (LCN). IEEE.
PreprintBibtex
@inproceedings{engel2015ahsalpwsncda, title = {A Heterogeneous System Architecture for Low-Power Wireless Sensor Nodes in Compute-intensive Distributed Applications}, author = {Engel, Andreas and Siebel, Thomas and Koch, Andreas}, booktitle = {IEEE Proc. Conference on Local Computer Networks (LCN)}, year = {2015}, organization = {IEEE} }
- Oppermann, J., Koch, A., Yu, T., and Sinnen, O. (2015). Domain-specific Optimisation for the High-level Synthesis of CellML-based Simulation Accelerators. In IEEE Proc. Intl. Conf. on Field Programmable Logic and Applications (FPL). IEEE.
Preprint SlidesBibtex
@inproceedings{oppermann2015dohscmlsa, title = {Domain-specific Optimisation for the High-level Synthesis of CellML-based Simulation Accelerators}, author = {Oppermann, Julian and Koch, Andreas and Yu, Ting and Sinnen, Oliver}, booktitle = {IEEE Proc. Intl. Conf. on Field Programmable Logic and Applications (FPL)}, year = {2015}, organization = {IEEE} }
- Engel, A., Hildebrand, P., Pott, P., Schlaak, F., and Koch, A. (2014). Hardware-Accelerated Embedded Controller for a Piezo-electric Haptic Feedback System. In Proc. 14th International Conference on New Actuators and Drive Systems.
PreprintBibtex
@inproceedings{engel2014haecphfs, title = {Hardware-Accelerated Embedded Controller for a Piezo-electric Haptic Feedback System}, author = {Engel, Andreas and Hildebrand, Paul and Pott, P. and Schlaak, F. and Koch, Andreas}, booktitle = {Proc. 14th International Conference on New Actuators and Drive Systems}, year = {2014} }
- Engel, A., and Koch, A. (2014). Hardware-Accelerated Data Compression in Low-Power Wireless Sensor Networks. In LNCS Proc. 10th International Symposium on Applied Reconfigurable Computing (ARC). LNCS.
PreprintBibtex
@inproceedings{engel2014hadclpwsn, title = {Hardware-Accelerated Data Compression in Low-Power Wireless Sensor Networks}, author = {Engel, Andreas and Koch, Andreas}, booktitle = {LNCS Proc. 10th International Symposium on Applied Reconfigurable Computing (ARC)}, year = {2014}, organization = {LNCS} }
- Hochberger, C., Jung, J., Engel, A., and Koch, A. (2014). Synthilation: JIT-Compilation of Microinstruction Sequences in AMIDAR Processors. In IEEE Proc. Conference on Design & Architectures for Signal & Image Processing (DASIP). IEEE.
PreprintBibtex
@inproceedings{hochberger2014sjitcmsamidarp, title = {Synthilation: JIT-Compilation of Microinstruction Sequences in AMIDAR Processors}, author = {Hochberger, Christian and Jung, Johannes and Engel, Andreas and Koch, Andreas}, booktitle = {IEEE Proc. Conference on Design & Architectures for Signal & Image Processing (DASIP)}, year = {2014}, organization = {IEEE} }
- Wink, T., and Koch, A. (2014). PHAT: A TECHNOLOGY FOR PROTOTYPING PARALLEL HETEROGENEOUS ARCHITECTURES. In IEEE Proc. Conference on Design & Architectures for Signal & Image Processing (DASIP). IEEE.
PreprintBibtex
@inproceedings{wink2014phatatechnologyforprototypingparallelheterogeneousarchitectures, title = {PHAT: A TECHNOLOGY FOR PROTOTYPING PARALLEL HETEROGENEOUS ARCHITECTURES}, author = {Wink, Thorsten and Koch, Andreas}, booktitle = {IEEE Proc. Conference on Design & Architectures for Signal & Image Processing (DASIP)}, year = {2014}, organization = {IEEE} }
- Huthmann, J., Oppermann, J., and Koch, A. (2014). Automatic high-level synthesis of multi-threaded hardware accelerators. In IEEE Proc. Intl. Conf. on Field Programmable Logic and Applications (FPL). IEEE.
PreprintBibtex
@inproceedings{huthmann2014a, title = {Automatic high-level synthesis of multi-threaded hardware accelerators}, author = {Huthmann, Jens and Oppermann, Julian and Koch, Andreas}, booktitle = {IEEE Proc. Intl. Conf. on Field Programmable Logic and Applications (FPL)}, year = {2014}, organization = {IEEE} }
- Liebig, B., and Koch, A. (2014). Low-Latency Double-Precision Floating-Point Division for FPGAs. In IEEE Proc. Intl. Conf. on Field-Programmable Technology (FPT). IEEE.
PreprintBibtex
@inproceedings{liebig2014lldpfpdfpga, title = {Low-Latency Double-Precision Floating-Point Division for FPGAs}, author = {Liebig, Björn and Koch, Andreas}, booktitle = {IEEE Proc. Intl. Conf. on Field-Programmable Technology (FPT)}, year = {2014}, organization = {IEEE} }
- Chevallerie, D. de la, Korinth, J., and Koch, A. (2014). Integrating FPGA-based Processing Elements into a Runtime for Parallel Heterogeneous Computing. In IEEE Proc. Intl. Conf. on Field-Programmable Technology (FPT). IEEE.
PreprintBibtex
@inproceedings{de2014ifpgaperphc, title = {Integrating FPGA-based Processing Elements into a Runtime for Parallel Heterogeneous Computing}, author = {de la Chevallerie, David and Korinth, Jens and Koch, Andreas}, booktitle = {IEEE Proc. Intl. Conf. on Field-Programmable Technology (FPT)}, year = {2014}, organization = {IEEE} }
- Engel, A., Friedmann, A., Koch, M., Rohlfing, J., Siebel, T., Mayer, D., and Koch, A. (2014). Hardware-Accelerated Wireless Sensor Network for Distributed Structural Health Monitoring. In Elsevier Procedia Technology (pp. 738–747).
PreprintBibtex
@inproceedings{engel2014hawsndshm, title = {Hardware-Accelerated Wireless Sensor Network for Distributed Structural Health Monitoring}, author = {Engel, Andreas and Friedmann, Andreas and Koch, Michael and Rohlfing, Jens and Siebel, Thomas and Mayer, Dirk and Koch, Andreas}, booktitle = {Elsevier Procedia Technology}, pages = {738--747}, year = {2014} }
- Engel, A., and Koch, A. (2014). An Energy-Efficient Wireless Routing Protocol for Distributed Structural Health Monitoring. In IEEE Proc. 7th IFIP Wireless and Mobile Networking Conference. IEEE.
PreprintBibtex
@inproceedings{engel2014aeewrpdshm, title = {An Energy-Efficient Wireless Routing Protocol for Distributed Structural Health Monitoring}, author = {Engel, Andreas and Koch, Andreas}, booktitle = {IEEE Proc. 7th IFIP Wireless and Mobile Networking Conference}, year = {2014}, organization = {IEEE} }
- Mühlbach, S., and Koch, A. (2014). A Reconfigurable Platform and Programming Tools for High-Level Network Applications Demonstrated as a Hardware Honeypot. In IEEE Journal on Selected Areas in Communications (pp. 1919–1932). IEEE.
PreprintBibtex
@inproceedings{muehlbach2014arppthlnadhh, title = {A Reconfigurable Platform and Programming Tools for High-Level Network Applications Demonstrated as a Hardware Honeypot}, author = {Mühlbach, Sascha and Koch, Andreas}, booktitle = {IEEE Journal on Selected Areas in Communications}, pages = {1919--1932}, year = {2014}, organization = {IEEE} }
- Stock, F., Hildenbrand, D., and Koch, A. (2013). FPGA-accelerated color edge detection using a Geometric-Algebra-to-Verilog compiler. In International Symposium on System on Chip (SoC) 2013.
PreprintBibtex
@inproceedings{stock2013fpga, title = {FPGA-accelerated color edge detection using a Geometric-Algebra-to-Verilog compiler}, author = {Stock, Florian and Hildenbrand, D. and Koch, Andreas}, booktitle = {International Symposium on System on Chip (SoC) 2013}, year = {2013} }
- Liebig, B., Huthmann, J., and Koch, A. (2013). Architecture Exploration of High-Performance Floating-Point Fused Multiply-Add. In Reconfigurable Architectures Workshop.
PreprintBibtex
@inproceedings{liebig2013aehp, title = {Architecture Exploration of High-Performance Floating-Point Fused Multiply-Add}, author = {Liebig, Björn and Huthmann, Jens and Koch, Andreas}, booktitle = {Reconfigurable Architectures Workshop}, year = {2013} }
- Huthmann, J., Liebig, B., Oppermann, J., and Koch, A. (2013). Hardware/software co-compilation with the Nymble system. In Proc. of the Intl. Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC).
PreprintBibtex
@inproceedings{huthmann2013hscc, title = {Hardware/software co-compilation with the Nymble system}, author = {Huthmann, Jens and Liebig, Björn and Oppermann, Julian and Koch, Andreas}, booktitle = {Proc. of the Intl. Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)}, year = {2013} }
- Thielmann, B., Huthmann, J., and Koch, A. (2012). Memory Latency Hiding by Load Value Speculation for Reconfigurable Computers. In ACM Transactions on Reconfigurable Technology and Systems. ACM.
PreprintBibtex
@inproceedings{thielmann2012mlhlvsrc, title = {Memory Latency Hiding by Load Value Speculation for Reconfigurable Computers}, author = {Thielmann, B. and Huthmann, Jens and Koch, Andreas}, booktitle = {ACM Transactions on Reconfigurable Technology and Systems}, year = {2012}, organization = {ACM} }
- Engel, A., Liebig, B., and Koch, A. (2012). Energy-efficient Heterogeneous Reconfigurable Sensor Node for Distributed Structural Health Monitoring. In IEEE Proc. Conference on Design & Architectures for Signal & Image Processing, 10-2012. IEEE.
PreprintBibtex
@inproceedings{engel2012ehrsndshm, title = {Energy-efficient Heterogeneous Reconfigurable Sensor Node for Distributed Structural Health Monitoring}, author = {Engel, Andreas and Liebig, Björn and Koch, Andreas}, booktitle = {IEEE Proc. Conference on Design & Architectures for Signal & Image Processing, 10-2012}, year = {2012}, organization = {IEEE} }
- Engel, A., Liebig, B., and Koch, A. (2012). HaLOEWEn: A Heterogeneous Reconfigurable Sensor Node for Distributed Structural Health Monitoring. In IEEE Proc. Conference on Design & Architectures for Signal & Image Processing, 10-2012
. IEEE.
PreprintBibtex
@inproceedings{engel2012hloeweahrsndshm, title = {HaLOEWEn: A Heterogeneous Reconfigurable Sensor Node for Distributed Structural Health Monitoring}, author = {Engel, Andreas and Liebig, Björn and Koch, Andreas}, booktitle = {IEEE Proc. Conference on Design & Architectures for Signal & Image Processing, 10-2012
}, year = {2012}, organization = {IEEE} } - Muehlbach, S., and Koch, A. (2012). Malacoda: Towards High-Level Compilation of Network Security Applications on Reconfigurable Hardware. In ACM/IEEE Proc. Symposium on Architectures for Networking and Communications Systems. ACM/IEEE.
PreprintBibtex
@inproceedings{muehlbach2012mthlcnsarh, title = {Malacoda: Towards High-Level Compilation of Network Security Applications on Reconfigurable Hardware}, author = {Muehlbach, S. and Koch, Andreas}, booktitle = {ACM/IEEE Proc. Symposium on Architectures for Networking and Communications Systems}, year = {2012}, organization = {ACM/IEEE} }
- Thielmann, B., Huthmann, J., and Koch, A. (2012). Embedded Systems Design with FPGAs. In P. Athanas, D. Pnevmatikatos, and N. Sklavos (Eds.), .
PreprintBibtex
@inbook{thielmann2012wmbacassm, chapter = {Widening the Memory Bottleneck by Automatically-Compiled Application-Specific Speculation Mechanisms}, author = {Thielmann, B. and Huthmann, Jens and Koch, Andreas}, editor = {Athanas, P. and Pnevmatikatos, D. and Sklavos, N.}, title = {Embedded Systems Design with FPGAs}, year = {2012} }
- Mühlbach, S., and Koch, A. (2012). A Dynamically Reconfigured Network Platform for High-Speed Malware Collection. In International Journal of Reconfigurable Computing.
PreprintBibtex
@inproceedings{muehlbach2012adrnphsmc, title = {A Dynamically Reconfigured Network Platform for High-Speed Malware Collection}, author = {Mühlbach, Sascha and Koch, Andreas}, booktitle = {International Journal of Reconfigurable Computing}, year = {2012} }
- Mühlbach, S., and Koch, A. (2011). A Reconfigurable Hardware Platform for Secure and Efficient Malware Collection in Next-Generation High-Speed Networks. In International Journal for Information Security Research.
PreprintBibtex
@inproceedings{muehlbach2011arhpsemcnghsn, title = {A Reconfigurable Hardware Platform for Secure and Efficient Malware Collection in Next-Generation High-Speed Networks}, author = {Mühlbach, Sascha and Koch, Andreas}, booktitle = {International Journal for Information Security Research}, year = {2011} }
- Thielmann, B., Huthmann, J., Wink, T., and Koch, A. (2011). RAP: More Efficient Memory Access in Highly Speculative Execution on Reconfigurable Adaptive Computers. In IEEE Proc. International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE.
PreprintBibtex
@inproceedings{thielmann2011rapmemahserac, title = {RAP: More Efficient Memory Access in Highly Speculative Execution on Reconfigurable Adaptive Computers}, author = {Thielmann, B. and Huthmann, Jens and Wink, Thorsten and Koch, Andreas}, booktitle = {IEEE Proc. International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, year = {2011}, organization = {IEEE} }
- Thielmann, B., Huthmann, J., and Koch, A. (2011). PreCoRe – A Token-based Speculation Architecture For High-Level Language to Hardware Compilation. In IEEE Proc. Intl. Conf. on Field Programmable Logic and Applications (FPL). IEEE.
PreprintBibtex
@inproceedings{thielmann2011pcratsafhllhc, title = {PreCoRe -- A Token-based Speculation Architecture For High-Level Language to Hardware Compilation}, author = {Thielmann, B. and Huthmann, Jens and Koch, Andreas}, booktitle = {IEEE Proc. Intl. Conf. on Field Programmable Logic and Applications (FPL)}, year = {2011}, organization = {IEEE} }
- Janda, O., Liebig, B., Lange, H., Konigorski, U., and Koch, A. (2011). Design and Hardware Implementation of a Controller for Active Damping of a Smart Structure. In Proc. 14th Intl. Adaptronic Congress.
PreprintBibtex
@inproceedings{janda2011dhicadss, title = {Design and Hardware Implementation of a Controller for Active Damping of a Smart Structure}, author = {Janda, O. and Liebig, Björn and Lange, Holger and Konigorski, U. and Koch, Andreas}, booktitle = {Proc. 14th Intl. Adaptronic Congress}, year = {2011} }
- Thielmann, B., Huthmann, J., and Koch, A. (2011). Evaluation of Speculative Execution Techniques for High-Level Language to Hardware Compilation. In IEEE Proc. 6th Intl. Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC). IEEE.
PreprintBibtex
@inproceedings{thielmann2011esethllhc, title = {Evaluation of Speculative Execution Techniques for High-Level Language to Hardware Compilation}, author = {Thielmann, B. and Huthmann, Jens and Koch, Andreas}, booktitle = {IEEE Proc. 6th Intl. Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)}, year = {2011}, organization = {IEEE} }
- Mühlbach, S., and Koch, A. (2011). A Scalable Multi-FPGA Platform for Complex Networking Applications. In IEEE 19th Annual Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE.
PreprintBibtex
@inproceedings{muehlbach2011asmfpgapcna, title = {A Scalable Multi-FPGA Platform for Complex Networking Applications}, author = {Mühlbach, Sascha and Koch, Andreas}, booktitle = {IEEE 19th Annual Symposium on Field-Programmable Custom Computing Machines (FCCM)}, year = {2011}, organization = {IEEE} }
- Engel, A., Liebig, B., and Koch, A. (2011). Feasibility Analysis of Reconfigurable Computing in Low-Power Wireless Sensor Applications. In LNCS Proc. 7th International Symposium on Applied Reconfigurable Computing (ARC). LNCS.
PreprintBibtex
@inproceedings{engel2011farclpwsa, title = {Feasibility Analysis of Reconfigurable Computing in Low-Power Wireless Sensor Applications}, author = {Engel, Andreas and Liebig, Björn and Koch, Andreas}, booktitle = {LNCS Proc. 7th International Symposium on Applied Reconfigurable Computing (ARC)}, year = {2011}, organization = {LNCS} }
- Mühlbach, S., and Koch, A. (2011). NetStage/DPR: A Self-Adaptable FPGA Platform for Application-Level Network Security. In LNCS Proc. 7th International Symposium on Applied Reconfigurable Computing (ARC). LNCS.
PreprintBibtex
@inproceedings{muehlbach2011nsdprasafpgapalns, title = {NetStage/DPR: A Self-Adaptable FPGA Platform for Application-Level Network Security}, author = {Mühlbach, Sascha and Koch, Andreas}, booktitle = {LNCS Proc. 7th International Symposium on Applied Reconfigurable Computing (ARC)}, year = {2011}, organization = {LNCS} }
- Koch, A., Krishnamurthy, R., McAllister, J., Woods, R., and El-Ghazawi, T. (2011). Reconfigurable Computing: Architectures, Tools and Applications. In Lecture Notes in Computer Science 6578.
Bibtex
@inproceedings{koch2011rcata, title = {Reconfigurable Computing: Architectures, Tools and Applications}, author = {Koch, Andreas and Krishnamurthy, R. and McAllister, J. and Woods, R. and El-Ghazawi, T.}, booktitle = {Lecture Notes in Computer Science 6578}, year = {2011} }
- Lange, H., Wink, T., and Koch, A. (2011). MARC II: A Parametrized Speculative Multi-Ported Memory Subsystem for Reconfigurable Computers. In ACM Proc. Design, Automation, and Test in Europe (DATE). ACM.
PreprintBibtex
@inproceedings{lange2011marciiapsmpmsrc, title = {MARC II: A Parametrized Speculative Multi-Ported Memory Subsystem for Reconfigurable Computers}, author = {Lange, Holger and Wink, Thorsten and Koch, Andreas}, booktitle = {ACM Proc. Design, Automation, and Test in Europe (DATE)}, year = {2011}, organization = {ACM} }
- Mühlbach, S., and Koch, A. (2011). A Novel Network Platform for Secure and Efficient Malware Collection based on Reconfigurable Hardware Logic. In IEEE Proc. World Congress on Internet Security (WorldCIS). IEEE.
Best Paper Award PreprintBibtex
@inproceedings{muehlbach2011annpsemcrhl, title = {A Novel Network Platform for Secure and Efficient Malware Collection based on Reconfigurable Hardware Logic}, author = {Mühlbach, Sascha and Koch, Andreas}, booktitle = {IEEE Proc. World Congress on Internet Security (WorldCIS)}, year = {2011}, organization = {IEEE} }
- Huthmann, J., Müller, P., Stock, F., Hildenbrand, D., and Koch, A. (2010). Compiling Geometric Algebra Computations into Reconfigurable Hardware Accelerators. In Dagstuhl Seminar Proc. #10281 on Dynamically Reconfigurable Architectures.
PreprintBibtex
@inproceedings{huthmann2010cgacrha, title = {Compiling Geometric Algebra Computations into Reconfigurable Hardware Accelerators}, author = {Huthmann, Jens and Müller, Peter and Stock, Florian and Hildenbrand, D. and Koch, Andreas}, booktitle = {Dagstuhl Seminar Proc. #10281 on Dynamically Reconfigurable Architectures}, year = {2010} }
- Mühlbach, S., and Koch, A. (2010). A Dynamically Reconfigured Network Platform for High-Speed Malware Collection. In IEEE Proc. Intl. Conf. on ReConFigurable Computing and FPGAs (ReConFig). IEEE.
PreprintBibtex
@inproceedings{muehlbach2010adrnphsmc, title = {A Dynamically Reconfigured Network Platform for High-Speed Malware Collection}, author = {Mühlbach, Sascha and Koch, Andreas}, booktitle = {IEEE Proc. Intl. Conf. on ReConFigurable Computing and FPGAs (ReConFig)}, year = {2010}, organization = {IEEE} }
- Stöttinger, M., Huss, S., Mühlbach, S., and Koch, A. (2010). Side-Channel Resistance Evaluation of a Neural Network Based Lightweight Cryptography Scheme. In IEEE Proc. Intl. Conf. on Embedded and Ubiquitous Computing (EUC). IEEE.
PreprintBibtex
@inproceedings{stoettinger2010scrennblcs, title = {Side-Channel Resistance Evaluation of a Neural Network Based Lightweight Cryptography Scheme}, author = {Stöttinger, M. and Huss, S. and Mühlbach, Sascha and Koch, Andreas}, booktitle = {IEEE Proc. Intl. Conf. on Embedded and Ubiquitous Computing (EUC)}, year = {2010}, organization = {IEEE} }
- Mühlbach, S., and Koch, A. (2010). An FPGA-based Scalable Platform for High-Speed Malware Collection in Large IP Networks. In IEEE Proc. Intl. Conf. on Field-Programmable Technology (FPT). IEEE.
PreprintBibtex
@inproceedings{muehlbach2010afpgasphsmclipn, title = {An FPGA-based Scalable Platform for High-Speed Malware Collection in Large IP Networks}, author = {Mühlbach, Sascha and Koch, Andreas}, booktitle = {IEEE Proc. Intl. Conf. on Field-Programmable Technology (FPT)}, year = {2010}, organization = {IEEE} }
- Lange, H., and Koch, A. (2010). Architectures and Execution Models for Hardware/Software Compilation and their System-Level Realization. In IEEE Transactions on Computers pp. 1363-1377. IEEE.
PreprintBibtex
@inproceedings{lange2010aemhscslr, title = {Architectures and Execution Models for Hardware/Software Compilation and their System-Level Realization}, author = {Lange, Holger and Koch, Andreas}, booktitle = {IEEE Transactions on Computers pp. 1363-1377}, year = {2010}, organization = {IEEE} }
- Hempel, G., Hochberger, C., and Koch, A. (2010). A Comparison of Hardware Acceleration Interfaces in a Customizable Soft Core Processor. In IEEE Proc. Intl. Conf. on Field Programmable Logic and Applications (FPL). IEEE.
PreprintBibtex
@inproceedings{hempel2010achaicscp, title = {A Comparison of Hardware Acceleration Interfaces in a Customizable Soft Core Processor}, author = {Hempel, G. and Hochberger, C. and Koch, Andreas}, booktitle = {IEEE Proc. Intl. Conf. on Field Programmable Logic and Applications (FPL)}, year = {2010}, organization = {IEEE} }
- Mühlbach, S., Brunner, M., Roblee, C., and Koch, A. (2010). MalCoBox: Designing a 10 Gb/s Malware Collection Honeypot Using Reconfigurable Technology. In IEEE Proc. Intl. Conf. on Field Programmable Logic and Applications (FPL). IEEE.
PreprintBibtex
@inproceedings{muehlbach2010mcbdgmchurt, title = {MalCoBox: Designing a 10 Gb/s Malware Collection Honeypot Using Reconfigurable Technology}, author = {Mühlbach, Sascha and Brunner, M. and Roblee, C. and Koch, Andreas}, booktitle = {IEEE Proc. Intl. Conf. on Field Programmable Logic and Applications (FPL)}, year = {2010}, organization = {IEEE} }
- Gädke-Lütjens, H., Thielmann, B., and Koch, A. (2010). A Flexible Compute and Memory Infrastructure for High-Level Language to Hardware Compilation. In IEEE Intl. Conf. on Field Programmable Logic and Applications (FPL), Milano (I). IEEE.
Preprint Material MaterialBibtex
@inproceedings{gaedke-luetjens2010afcmihllhc, title = {A Flexible Compute and Memory Infrastructure for High-Level Language to Hardware Compilation}, author = {Gädke-Lütjens, H. and Thielmann, B. and Koch, Andreas}, booktitle = {IEEE Intl. Conf. on Field Programmable Logic and Applications (FPL), Milano (I)}, year = {2010}, organization = {IEEE} }
- Schwinn, C., Hildenbrand, D., Stock, F., and Koch, A. (2010). Gaalop 2.0 - A Geometric Algebra Algorithm Compiler. In Proc. Workshop on Computer Graphics, Computer Vision and Mathematics.
PreprintBibtex
@inproceedings{schwinn2010gagaac, title = {Gaalop 2.0 - A Geometric Algebra Algorithm Compiler}, author = {Schwinn, C. and Hildenbrand, D. and Stock, Florian and Koch, Andreas}, booktitle = {Proc. Workshop on Computer Graphics, Computer Vision and Mathematics}, year = {2010} }
- Huthmann, J., Müller, P., Stock, F., Hildenbrand, D., and Koch, A. (2010). Accelerating High-Level Engineering Computations by Automatic Compilation of Geometric Algebra to Hardware Accelerators. In IEEE Proc. Intl. Conf. on Embedded Computer Systems: Architectures, MOdeling and Simulation (SAMOS). IEEE.
PreprintBibtex
@inproceedings{huthmann2010ahlecacgaha, title = {Accelerating High-Level Engineering Computations by Automatic Compilation of Geometric Algebra to Hardware Accelerators}, author = {Huthmann, Jens and Müller, Peter and Stock, Florian and Hildenbrand, D. and Koch, Andreas}, booktitle = {IEEE Proc. Intl. Conf. on Embedded Computer Systems: Architectures, MOdeling and Simulation (SAMOS)}, year = {2010}, organization = {IEEE} }
- Hildenbrand, D., Pitt, J., and Koch, A. (2010). Geometric Algebra Computing for Engineering and Computer Science. In E. Bayro-Corrochano and G. Scheuermann (Eds.), .
PreprintBibtex
@inbook{hildenbrand2010hpgacg, chapter = {High Performance Geometric Algebra Computing based on Gaalop}, author = {Hildenbrand, D. and Pitt, J. and Koch, Andreas}, title = {Geometric Algebra Computing for Engineering and Computer Science}, editor = {Bayro-Corrochano, E. and Scheuermann, G.}, year = {2010} }
- Koch, A. (2010). Dynamically Reconfigurable Systems. In M. Platzner, J. Teich, and N. Wehn (Eds.), .
PreprintBibtex
@inbook{koch2010acsdt, chapter = {Adaptive Computing Systems and their Design Tools}, author = {Koch, Andreas}, title = {Dynamically Reconfigurable Systems}, editor = {Platzner, M. and Teich, J. and Wehn, N.}, year = {2010} }
- Hochberger, C., and Koch, A. (2009). Challenges of Electronic CAD in the Nano Scale Era. In GI LNI Workshop Grand Challenges der technischen Informatik. GI.
PreprintBibtex
@inproceedings{hochberger2009cecadnse, title = {Challenges of Electronic CAD in the Nano Scale Era}, author = {Hochberger, C. and Koch, Andreas}, booktitle = {GI LNI Workshop Grand Challenges der technischen Informatik}, year = {2009}, organization = {GI} }
- Stock, F., and Koch, A. (2009). A Fast GPU Implementation for Solving Sparse Ill-Posed Linear Equation Systems. In LNCS Proc. of Eighth International Conference on Parallel Processing and Mathematics. LNCS.
Preprint The original publication is available at www.springerlink.comBibtex
@inproceedings{stock2009afgpuissiples, title = {A Fast GPU Implementation for Solving Sparse Ill-Posed Linear Equation Systems}, author = {Stock, Florian and Koch, Andreas}, booktitle = {LNCS Proc. of Eighth International Conference on Parallel Processing and Mathematics}, year = {2009}, organization = {LNCS}, springer = {http://www.springerlink.com/content/288560u268w77034} }
- Lange, H., Stock, F., Koch, A., and Hildenbrand, D. (2009). Acceleration and Energy Efficiency of a Geometric Algebra Computation using Reconfigurable Computers and GPUs. In IEEE Seventeenth Annual Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE.
PreprintBibtex
@inproceedings{lange2009aeegacrcgpu, title = {Acceleration and Energy Efficiency of a Geometric Algebra Computation using Reconfigurable Computers and GPUs}, author = {Lange, Holger and Stock, Florian and Koch, Andreas and Hildenbrand, D.}, booktitle = {IEEE Seventeenth Annual Symposium on Field-Programmable Custom Computing Machines (FCCM)}, year = {2009}, organization = {IEEE} }
- Lange, H., and Koch, A. (2008). Low-Latency High-Bandwidth HW/SW Communication in a Virtual Memory Environment. In IEEE Intl. Conf. on Field Programmable Logic and Applications (FPL). IEEE.
PreprintBibtex
@inproceedings{lange2008llhbhwswcvme, title = {Low-Latency High-Bandwidth HW/SW Communication in a Virtual Memory Environment}, author = {Lange, Holger and Koch, Andreas}, booktitle = {IEEE Intl. Conf. on Field Programmable Logic and Applications (FPL)}, year = {2008}, organization = {IEEE} }
- Gädke, H., Stock, F., and Koch, A. (2008). Memory Access Parallelization in High-Level Language Compilation for Reconfigurable Adaptive Computers. In IEEE Intl. Conf. on Field Programmable Logic and Applications (FPL). IEEE.
PreprintBibtex
@inproceedings{gaedke2008maphllcrac, title = {Memory Access Parallelization in High-Level Language Compilation for Reconfigurable Adaptive Computers}, author = {Gädke, H. and Stock, Florian and Koch, Andreas}, booktitle = {IEEE Intl. Conf. on Field Programmable Logic and Applications (FPL)}, year = {2008}, organization = {IEEE} }
- Rekonfigurierbare Architekturen. (2008). In GI Informatik Spektrum. GI.
Bibtex
@inproceedings{berekovic2008ra, title = {Rekonfigurierbare Architekturen}, author = {}, booktitle = {GI Informatik Spektrum}, year = {2008}, organization = {GI} }
- Gädke, H., and Koch, A. (2008). Accelerating Speculative Execution in High-Level Synthesis with Cancel Tokens. In LNCS Intl. Workshop on Applied Reconfigurable Computing. LNCS.
PreprintBibtex
@inproceedings{gaedke2008asehlsct, title = {Accelerating Speculative Execution in High-Level Synthesis with Cancel Tokens}, author = {Gädke, H. and Koch, Andreas}, booktitle = {LNCS Intl. Workshop on Applied Reconfigurable Computing}, year = {2008}, organization = {LNCS} }
- Nagel, W. E., Hoffmann, R., and Koch, A. (2008). Proceedings of the 9th Workshop on Parallel Systems and Algorithms (PASA). In GI Lecture Notes in Informatics No. 124. GI.
Bibtex
@inproceedings{nagel2008pwpsapasa, title = {Proceedings of the 9th Workshop on Parallel Systems and Algorithms (PASA)}, author = {Nagel, W. E. and Hoffmann, R. and Koch, Andreas}, booktitle = {GI Lecture Notes in Informatics No. 124}, year = {2008}, organization = {GI} }
- Hildenbrand, D., Lange, H., Stock, F., and Koch, A. (2008). Efficient Inverse Kinematics Algorithm based on Conformal Geometric Algebra Using Reconfigurable Hardware. In Intl. Conf. on Computer Graphics Theory and Applications (GRAPP). GRAPP.
PreprintBibtex
@inproceedings{hildenbrand2008eikacgaurh, title = {Efficient Inverse Kinematics Algorithm based on Conformal Geometric Algebra Using Reconfigurable Hardware}, author = {Hildenbrand, D. and Lange, Holger and Stock, Florian and Koch, Andreas}, booktitle = {Intl. Conf. on Computer Graphics Theory and Applications (GRAPP)}, year = {2008}, organization = {GRAPP} }
- Koch, A. (2008). Reconfigurable Computing. In S. Hauck and A. DeHon (Eds.), .
Bibtex
@inbook{koch2008dc, chapter = {Datapath Composition}, author = {Koch, Andreas}, title = {Reconfigurable Computing}, editor = {Hauck, S. and DeHon, A}, year = {2008} }
- Gädke, H., and Koch, A. (2007). Comrade - A Compiler for Adaptive Computing Systems Using a Novel Fast Speculation Technique. In IEEE Intl. Conf. on Field Programmable Logic and Applications (FPL). IEEE.
PreprintBibtex
@inproceedings{gaedke2007cacacsunfst, title = {Comrade - A Compiler for Adaptive Computing Systems Using a Novel Fast Speculation Technique}, author = {Gädke, H. and Koch, Andreas}, booktitle = {IEEE Intl. Conf. on Field Programmable Logic and Applications (FPL)}, year = {2007}, organization = {IEEE} }
- Lange, H., and Koch, A. (2007). An Execution Model for Hardware/Software Compilation and its System-Level Realization. In IEEE Intl. Conf. on Field Programmable Logic and Applications (FPL). IEEE.
PreprintBibtex
@inproceedings{lange2007aemhscslr, title = {An Execution Model for Hardware/Software Compilation and its System-Level Realization}, author = {Lange, Holger and Koch, Andreas}, booktitle = {IEEE Intl. Conf. on Field Programmable Logic and Applications (FPL)}, year = {2007}, organization = {IEEE} }
- Gädke, H., and Koch, A. (2007). Comrade - A Compiler for Adaptive Systems. In Design, Automation and Test in Europe (DATE), Conference & Exhibition. DATE.
PreprintBibtex
@inproceedings{gaedke2007cacas, title = {Comrade - A Compiler for Adaptive Systems}, author = {Gädke, H. and Koch, Andreas}, booktitle = {Design, Automation and Test in Europe (DATE), Conference & Exhibition}, year = {2007}, organization = {DATE} }
- Platzner, M., Großpietsch, K., Hochberger, C., and Koch, A. (2007). ARCS ’07 - 20th International Conference on Architecture of Computing Systems 2007. In Workshop Proceedings. ARCS.
Bibtex
@inproceedings{platzner2007arcsicacs, title = {ARCS '07 - 20th International Conference on Architecture of Computing Systems 2007}, author = {Platzner, M. and Großpietsch, K. and Hochberger, C. and Koch, Andreas}, booktitle = {Workshop Proceedings}, year = {2007}, organization = {ARCS} }
- Lange, H., and Koch, A. (2007). Design and System Level Evaluation of a High Performance Memory System for reconfigurable SoC Platforms. In Proc. HiPEAC Workshop on Reconfigurable Computing. HiPEAC.
PreprintBibtex
@inproceedings{lange2007dslehpmsscp, title = {Design and System Level Evaluation of a High Performance Memory System for reconfigurable SoC Platforms}, author = {Lange, Holger and Koch, Andreas}, booktitle = {Proc. HiPEAC Workshop on Reconfigurable Computing}, year = {2007}, organization = {HiPEAC} }
- Koch, A. (2007). Efficient Integration of Pipelined IP Blocks into Automatically Compiled Datapaths. In EURASIP Journal on Embedded Systems, 2007 Special Issue on Dynamically Reconfigurable Systems. EURASIP.
PreprintBibtex
@inproceedings{koch2007eipipbacd, title = {Efficient Integration of Pipelined IP Blocks into Automatically Compiled Datapaths}, author = {Koch, Andreas}, booktitle = {EURASIP Journal on Embedded Systems, 2007 Special Issue on Dynamically Reconfigurable Systems.}, year = {2007}, organization = {EURASIP} }
- Koch, A., Leong, P., and Boemo, E. (2006). Proceedings of the 2006 International Conference on Field-Programmable Logic and Applications. In IEEE, 2006. IEEE.
Bibtex
@inproceedings{koch2006picfpla, title = {Proceedings of the 2006 International Conference on Field-Programmable Logic and Applications}, author = {Koch, Andreas and Leong, P. and Boemo, E.}, booktitle = {IEEE, 2006}, year = {2006}, organization = {IEEE} }
- Stock, F., and Koch, A. (2006). Architecture Exploration and Tools for Pipelined Coarse-grained Reconfigurable Arrays. In IEEE Intl. Conf. On Field-Programmable Logic (FPL). IEEE.
PreprintBibtex
@inproceedings{stock2006aetpcra, title = {Architecture Exploration and Tools for Pipelined Coarse-grained Reconfigurable Arrays}, author = {Stock, Florian and Koch, Andreas}, booktitle = {IEEE Intl. Conf. On Field-Programmable Logic (FPL)}, year = {2006}, organization = {IEEE} }
- Kasprzyk, N., Veen, J. C. van der, and Koch, A. (2005). Configuration Merging for Adaptive Computer Applications. In IEEE Intl. Conf. On Field-Programmable Logic (FPL). IEEE.
PreprintBibtex
@inproceedings{kasprzyk2005cmaca, title = {Configuration Merging for Adaptive Computer Applications}, author = {Kasprzyk, N. and van der Veen, J. C. and Koch, Andreas}, booktitle = {IEEE Intl. Conf. On Field-Programmable Logic (FPL)}, year = {2005}, organization = {IEEE} }
- Kasprzyk, N., and Koch, A. (2005). High-Level-Language Compilation for Reconfigurable Computers. In Intl. Conf. on Reconfigurable Communication-centric SoCs.
PreprintBibtex
@inproceedings{kasprzyk2005hllcrc, title = {High-Level-Language Compilation for Reconfigurable Computers}, author = {Kasprzyk, N. and Koch, Andreas}, booktitle = {Intl. Conf. on Reconfigurable Communication-centric SoCs}, year = {2005} }
- Koch, A. (2004). Advances in Adaptive Computer Technology (habilitation). Tech. Univ. Braunschweig, Germany.
PreprintBibtex
@phdthesis{koch2004habil, type = {habilitation}, title = {Advances in Adaptive Computer Technology}, author = {Koch, Andreas}, school = {Tech. Univ. Braunschweig, Germany}, year = {2004}, organization = {Tech. Univ. Braunschweig, Germany} }
- Kasprzyk, N., and Koch, A. (2004). Verbesserte Hardware-Software-Partitionierung für Adaptive Computer. In GI Architecture of Computing Systems (ARCS): Workshop on Dynamically Reconfigurable Systems.
PreprintBibtex
@inproceedings{koch2004vhspac, title = {Verbesserte Hardware-Software-Partitionierung für Adaptive Computer}, author = {Kasprzyk, N. and Koch, Andreas}, booktitle = {GI Architecture of Computing Systems (ARCS): Workshop on Dynamically Reconfigurable Systems}, year = {2004} }
- Rock, M., and Koch, A. (2004). Architecture-Independent Meta-Optimization by Aggressive Tail Splitting. In LNCS Euro-Par Conference. LNCS.
PreprintBibtex
@inproceedings{koch2004aimoats, title = {Architecture-Independent Meta-Optimization by Aggressive Tail Splitting}, author = {Rock, M. and Koch, Andreas}, booktitle = {LNCS Euro-Par Conference}, year = {2004}, organization = {LNCS} }
- Gädke, H., and Koch, A. (2004). Wavelet-based Image Compression on the Reconfigurable Computer ACE-V. In LNCS Intl. Conf. On Field-Programmable Logic (FPL). LNCS.
PreprintBibtex
@inproceedings{koch2004wicrc, title = {Wavelet-based Image Compression on the Reconfigurable Computer ACE-V}, author = {Gädke, H. and Koch, Andreas}, booktitle = {LNCS Intl. Conf. On Field-Programmable Logic (FPL)}, year = {2004}, organization = {LNCS} }
- Lange, H., and Koch, A. (2004). Hardware/Software-Codesign by Automatic Embedding of Complex IP Cores. In LNCS Intl. Conf. On Field-Programmable Logic (FPL). LNCS.
PreprintBibtex
@inproceedings{lange2004hscaec, title = {Hardware/Software-Codesign by Automatic Embedding of Complex IP Cores}, author = {Lange, Holger and Koch, Andreas}, booktitle = {LNCS Intl. Conf. On Field-Programmable Logic (FPL)}, year = {2004}, organization = {LNCS} }
- Schmidt, C., and Koch, A. (2003). Fast Region Labeling on the Reconfigurable Platform ACE-V. In LNCS Workshop on Field Programmable Logic and Applications. LNCS.
PreprintBibtex
@inproceedings{koch2003frlrp, title = {Fast Region Labeling on the Reconfigurable Platform ACE-V}, author = {Schmidt, C. and Koch, Andreas}, booktitle = {LNCS Workshop on Field Programmable Logic and Applications}, year = {2003}, organization = {LNCS} }
- Koch, A. (2003). Compilation for Adaptive Computers: Experiences and Opportunities. In IBFI-Seminar Dynamically Reconfigurable Architectures.
PreprintBibtex
@inproceedings{koch2003caceo, title = {Compilation for Adaptive Computers: Experiences and Opportunities}, author = {Koch, Andreas}, booktitle = {IBFI-Seminar Dynamically Reconfigurable Architectures}, year = {2003} }
- Kasprzyk, N., Koch, A., Golze, U., and Rock, M. (2003). An Improved Intermediate Representation for Datapath Generation. In International Conference on Engineering of Reconfigurable Systems and Algorithms.
PreprintBibtex
@inproceedings{koch2003aiirdg, title = {An Improved Intermediate Representation for Datapath Generation}, author = {Kasprzyk, N. and Koch, Andreas and Golze, U. and Rock, M.}, booktitle = {International Conference on Engineering of Reconfigurable Systems and Algorithms}, year = {2003} }
- Koch, A. (2003). Tutorial: Reconfigurable Computing - Fundamentals, Architectures, and Tools. In Conference on Design Automation and Test in Europe (DATE).
PreprintBibtex
@inproceedings{koch2003tutorial, title = {Tutorial: Reconfigurable Computing - Fundamentals, Architectures, and Tools}, author = {Koch, Andreas}, booktitle = {Conference on Design Automation and Test in Europe (DATE)}, year = {2003} }
- Kasprzyk, N., Koch, A., Golze, U., and Rock, M. (2003). Eine effiziente Kontrollfluss-Repräsentation für die Erzeugung von Datenpfaden. In 11. E.I.S. Workshop. E.I.S.
PreprintBibtex
@inproceedings{koch2003ekred, title = {Eine effiziente Kontrollfluss-Repräsentation für die Erzeugung von Datenpfaden}, author = {Kasprzyk, N. and Koch, Andreas and Golze, U. and Rock, M.}, booktitle = {11. E.I.S. Workshop}, year = {2003}, organization = {E.I.S.} }
- Koch, A., and Kasprzyk, N. (2002). Module Generators Driving the Compilation for Adaptive Computing Systems. In IEEE International Symposium on FCCMs. IEEE.
Bibtex
@inproceedings{koch2002mgdcacs, title = {Module Generators Driving the Compilation for Adaptive Computing Systems}, author = {Koch, Andreas and Kasprzyk, N.}, booktitle = {IEEE International Symposium on FCCMs}, year = {2002}, organization = {IEEE} }
- Koch, A. (2002). Architectures and Tools for Heterogeneous Reconfigurable Systems. In IEEE Workshop on Heterogeneous Reconfigurable Systems-on-Chip. IEEE.
PreprintBibtex
@inproceedings{koch2002athrs, title = {Architectures and Tools for Heterogeneous Reconfigurable Systems}, author = {Koch, Andreas}, booktitle = {IEEE Workshop on Heterogeneous Reconfigurable Systems-on-Chip}, year = {2002}, organization = {IEEE} }
- Koch, A. (2002). Compilation for Adaptive Computing Systems Using Complex Parameterized Hardware Objects. In Kluwer Journal of Supercomputing 21 (pp. 179–190).
PreprintBibtex
@inproceedings{koch2002cacsucpho, title = {Compilation for Adaptive Computing Systems Using Complex Parameterized Hardware Objects}, author = {Koch, Andreas}, booktitle = {Kluwer Journal of Supercomputing 21}, pages = {179--190}, year = {2002} }
- Neumann, T., and Koch, A. (2001). A Generic Library for Adaptive Computing Environments. In LNCS Workshop on Field-Programmable Logic and Applications, Belfast, 08-2001. LNCS.
PreprintBibtex
@inproceedings{koch2001aglace, title = {A Generic Library for Adaptive Computing Environments}, author = {Neumann, T. and Koch, Andreas}, booktitle = {LNCS Workshop on Field-Programmable Logic and Applications, Belfast, 08-2001.}, year = {2001}, organization = {LNCS} }
- Kasprzyk, N., and Koch, A. (2001). Advances in Compiler Construction for Adaptive Computers. In International Conference on Parallel and Distributed Processing Techniques and Applications.
PreprintBibtex
@inproceedings{koch2001accac, title = {Advances in Compiler Construction for Adaptive Computers}, author = {Kasprzyk, N. and Koch, Andreas}, booktitle = {International Conference on Parallel and Distributed Processing Techniques and Applications}, year = {2001} }
- Koch, A. (2001). Adaptive Rechensysteme und ihre Entwurfswerkzeuge. In 10. E.I.S.-Workshop. E.I.S.
PreprintBibtex
@inproceedings{koch2001are, title = {Adaptive Rechensysteme und ihre Entwurfswerkzeuge}, author = {Koch, Andreas}, booktitle = {10. E.I.S.-Workshop}, year = {2001}, organization = {E.I.S.} }
- Lange, H., and Koch, A. (2000). Memory Access Schemes for Configurable Processors. In LNCS Intl. Workshop on Field-Programmable Logic and Applications. LNCS.
PreprintBibtex
@inproceedings{koch2000mascp, title = {Memory Access Schemes for Configurable Processors}, author = {Lange, Holger and Koch, Andreas}, booktitle = {LNCS Intl. Workshop on Field-Programmable Logic and Applications}, year = {2000}, organization = {LNCS} }
- Koch, A. (2000). Creation and Embedding of Complex Parameterized Hardware Objects. In LNCS Workshop on Engineering of Reconfigurable Hardware/Software Objects. LNCS.
PreprintBibtex
@inproceedings{koch2000cecpho, title = {Creation and Embedding of Complex Parameterized Hardware Objects}, author = {Koch, Andreas}, booktitle = {LNCS Workshop on Engineering of Reconfigurable Hardware/Software Objects}, year = {2000}, organization = {LNCS} }
- Koch, A. (2000). A Comprehensive Prototyping Platform for Hardware-Software Codesign. In IEEE Workshop on Rapid Systems Prototyping. IEEE.
PreprintBibtex
@inproceedings{koch2000hsc, title = {A Comprehensive Prototyping Platform for Hardware-Software Codesign}, author = {Koch, Andreas}, booktitle = {IEEE Workshop on Rapid Systems Prototyping}, year = {2000}, organization = {IEEE} }
- Koch, A. (1999). Adaptive Rechensysteme - Architekturen und Werkzeuge. In 9. E.I.S.-Workshop. E.I.S.
PreprintBibtex
@inproceedings{koch1999arauw, title = {Adaptive Rechensysteme - Architekturen und Werkzeuge.}, author = {Koch, Andreas}, booktitle = {9. E.I.S.-Workshop}, year = {1999}, organization = {E.I.S.} }
- Koch, A. (1999). On Tool Integration in High-Performance FPGA Design Flows. In LNCS Intl. Workshop on Field-Programmable Logic and Applications. LNCS.
PreprintBibtex
@inproceedings{koch1999hpfpga, title = {On Tool Integration in High-Performance FPGA Design Flows}, author = {Koch, Andreas}, booktitle = {LNCS Intl. Workshop on Field-Programmable Logic and Applications}, year = {1999}, organization = {LNCS} }
- Boege, M., and Koch, A. (1999). A Processor for Artificial Life Simulation. In LNCS Intl. Workshop on Field-Programmable Logic and Applications. LNCS.
PreprintBibtex
@inproceedings{koch1999als, title = {A Processor for Artificial Life Simulation}, author = {Boege, M. and Koch, Andreas}, booktitle = {LNCS Intl. Workshop on Field-Programmable Logic and Applications}, year = {1999}, organization = {LNCS} }
- Koch, A. (1999). Enabling Automatic Module Generation for FCCM Compilers. In IEEE Intl. Symposium on FCCMs. IEEE.
PreprintBibtex
@inproceedings{koch1999fccm, title = {Enabling Automatic Module Generation for FCCM Compilers}, author = {Koch, Andreas}, booktitle = {IEEE Intl. Symposium on FCCMs}, year = {1999}, organization = {IEEE} }
- Koch, A. (1999). Unified Access to Heterogeneous Module Generators. In Intl. Symposium on FPGAs. ACM.
Bibtex
@inproceedings{koch1999hmg, title = {Unified Access to Heterogeneous Module Generators}, author = {Koch, Andreas}, booktitle = {Intl. Symposium on FPGAs}, year = {1999}, organization = {ACM} }
- Koch, A. (1998). Generator-based Design Flows for Reconfigurable Computing: A Tutorial on Tool Integration using FLAME. In PACT98 Workshop on Reconfigurable Computing. PACT.
PreprintBibtex
@inproceedings{koch1998rcflame, title = {Generator-based Design Flows for Reconfigurable Computing: A Tutorial on Tool Integration using FLAME}, author = {Koch, Andreas}, booktitle = {PACT98 Workshop on Reconfigurable Computing}, year = {1998}, organization = {PACT} }
- Koch, A. (1998). Accessing Module Libraries (Talk). In ACS Principal Investigator Conference, Napa Valley (CA, USA), 04-1998.
Bibtex
@inproceedings{koch1998aml, title = {Accessing Module Libraries (Talk)}, author = {Koch, Andreas}, booktitle = {ACS Principal Investigator Conference, Napa Valley (CA, USA), 04-1998.}, year = {1998} }
- Koch, A. (1998). Proposal for inter-tool communication protocols in the ACS/NC System (Talk). In Synopsys Inc., Mountain View (CA, USA), 04-1998.
Bibtex
@inproceedings{koch1998intertool, title = {Proposal for inter-tool communication protocols in the ACS/NC System (Talk)}, author = {Koch, Andreas}, booktitle = {Synopsys Inc., Mountain View (CA, USA), 04-1998.}, year = {1998} }
- Koch, A. (1998). Efficient Datapath Composition for Coarse-Grained FPGAs (Talk). In Xilinx Inc., San Jose (CA, USA), 04-1998.
Bibtex
@inproceedings{koch1998cgfpga, title = {Efficient Datapath Composition for Coarse-Grained FPGAs (Talk)}, author = {Koch, Andreas}, booktitle = {Xilinx Inc., San Jose (CA, USA), 04-1998.}, year = {1998} }
- Koch, A. (1998). FLAME - A Flexible API for Module-based Environments (Talk). In 2nd ACS Project Review, Berkeley (CA, USA), 03-1998.
PreprintBibtex
@inproceedings{koch1998flame, title = {FLAME - A Flexible API for Module-based Environments (Talk)}, author = {Koch, Andreas}, booktitle = {2nd ACS Project Review, Berkeley (CA, USA), 03-1998.}, year = {1998} }
- Koch, A. (1998). Regular Datapaths on Field-Programmable Gate Arrays (Talk). In 3rd BRASS/IRAM Industrial Feedback Retreat.
PreprintBibtex
@inproceedings{koch1998fpga, title = {Regular Datapaths on Field-Programmable Gate Arrays (Talk)}, author = {Koch, Andreas}, booktitle = {3rd BRASS/IRAM Industrial Feedback Retreat}, year = {1998} }
- Koch, A. (1997). Practical Experiences with the SPARXIL Co-Processor. In IEEE 31st Asilomar Conference on Signals, Systems, and Computers. IEEE.
PreprintBibtex
@inproceedings{koch1997sparxil, title = {Practical Experiences with the SPARXIL Co-Processor}, author = {Koch, Andreas}, booktitle = {IEEE 31st Asilomar Conference on Signals, Systems, and Computers}, year = {1997}, organization = {IEEE} }
- Koch, A. (1997). Regular Datapaths on Field-Programmable Gate Arrays (dissertation). Tech. Univ. Braunschweig (Germany).
PreprintBibtex
@phdthesis{koch1997diss, type = {dissertation}, title = {Regular Datapaths on Field-Programmable Gate Arrays}, author = {Koch, Andreas}, school = {Tech. Univ. Braunschweig (Germany)}, year = {1997}, organization = {Tech. Univ. Braunschweig (Germany)} }
- Koch, A. (1997). Objekt-orientierte Modellierung von hybriden Hardware- Software-Systemen am Beispiel des "European Home System" (EHS) Standards. In 8. E.I.S. Workshop. E.I.S.
PreprintBibtex
@inproceedings{koch1997oo, title = {Objekt-orientierte Modellierung von hybriden Hardware- Software-Systemen am Beispiel des "European Home System" (EHS) Standards.}, author = {Koch, Andreas}, booktitle = {8. E.I.S. Workshop}, year = {1997}, organization = {E.I.S.} }
- Koch, A. (1996). Module Compaction in FPGA-based Regular Datapaths. In 33rd Design Automation Conference (DAC). ACM.
PreprintBibtex
@inproceedings{koch1996datapaths2, title = {Module Compaction in FPGA-based Regular Datapaths}, author = {Koch, Andreas}, booktitle = {33rd Design Automation Conference (DAC)}, year = {1996}, organization = {ACM} }
- Koch, A. (1996). Structured Design Implementation - A Strategy for Implementing Regular Datapaths on FPGAs. In 4th International Symposium on FPGAs (FPGA). ACM.
PreprintBibtex
@inproceedings{koch1996datapaths, title = {Structured Design Implementation - A Strategy for Implementing Regular Datapaths on FPGAs}, author = {Koch, Andreas}, booktitle = {4th International Symposium on FPGAs (FPGA)}, year = {1996}, organization = {ACM} }
- Koch, A. (1995). Effiziente Implementierung von Datenpfaden auf FPGAs. In 7. E.I.S. Workshop. E.I.S.
PreprintBibtex
@inproceedings{koch1995effizient, title = {Effiziente Implementierung von Datenpfaden auf FPGAs}, author = {Koch, Andreas}, booktitle = {7. E.I.S. Workshop}, year = {1995}, organization = {E.I.S.} }
- Koch, A. (1995). Structured Design Implementation - Eine Implementierungsstrategie für Datenpfade auf FPGAs. In GI/ITG Workshop "Anwenderprogrammierbare Schaltungen". GI/ITG.
PreprintBibtex
@inproceedings{koch1995datenpfade, title = {Structured Design Implementation - Eine Implementierungsstrategie für Datenpfade auf FPGAs}, author = {Koch, Andreas}, booktitle = {GI/ITG Workshop "Anwenderprogrammierbare Schaltungen"}, year = {1995}, organization = {GI/ITG} }
- Koch, A. (1994). More FPGAs. In W. Moore and W. Luk (Eds.), .
PreprintBibtex
@inbook{koch1994universal, chapter = {A Universal Co-Processor for Workstations}, author = {Koch, Andreas}, title = {More FPGAs}, editor = {Moore, W. and Luk, W}, year = {1994} }
- Koch, A. (1994). User-friendly FPGA Design with an Improved Cadence Opus - Xilinx XACT Interface. In 5th EUROCHIP Workshop. EUROCHIP.
PreprintBibtex
@inproceedings{koch1994cadence, title = {User-friendly FPGA Design with an Improved Cadence Opus - Xilinx XACT Interface}, author = {Koch, Andreas}, booktitle = {5th EUROCHIP Workshop}, year = {1994}, organization = {EUROCHIP} }
- Koch, A. (1994). SPARXIL: Ein konfigurierbarer FPGA-Coprozessor. In GI/ITG Workshop "Arch. für hochintegrierte Schaltungen". GI/ITG.
PreprintBibtex
@inproceedings{koch1994copro, title = {SPARXIL: Ein konfigurierbarer FPGA-Coprozessor}, author = {Koch, Andreas}, booktitle = {GI/ITG Workshop "Arch. für hochintegrierte Schaltungen"}, year = {1994}, organization = {GI/ITG} }
- Koch, A. (1993). An FPGA-based Co-Processor for SBus Workstations. In LNCS Proc. 3rd Conference on Field Programmable Logic and Applications (FPL). LNCS.
PreprintBibtex
@inproceedings{koch1993copro, title = {An FPGA-based Co-Processor for SBus Workstations}, author = {Koch, Andreas}, booktitle = {LNCS Proc. 3rd Conference on Field Programmable Logic and Applications (FPL)}, year = {1993}, organization = {LNCS} }
- Koch, A. (1993). FPGA Applications in Education and Research. In 4rd EUROCHIP Workshop (pp. 260–265).
PreprintBibtex
@inproceedings{koch1993app, title = {FPGA {A}pplications in {E}ducation and {R}esearch}, author = {Koch, Andreas}, booktitle = {4rd {EUROCHIP} {W}orkshop}, pages = {260--265}, year = {1993} }
- Koch, A. (1992). Experiences with the Framework Cadence Skill/IL. In Proc. 3rd EUROCHIP Workshop (pp. 118–123). EUROCHIP.
PreprintBibtex
@inproceedings{koch1992exp, title = {Experiences with the {F}ramework {C}adence {S}kill/{IL}}, author = {Koch, Andreas}, booktitle = {Proc. 3rd {EUROCHIP} {W}orkshop}, pages = {118--123}, year = {1992}, organization = {EUROCHIP} }
- Koch, A. (1992). Integrationssprachen in VLSI-Design-Frameworks am Beispiel von Cadence Skill/IL (Master's thesis). TU Braunschweig.
Bibtex
@mastersthesis{koch1992diplom, title = {Integrationssprachen in {VLSI}-{D}esign-{F}rameworks am {B}eispiel von {C}adence {S}kill/{IL}}, author = {Koch, Andreas}, year = {1992}, school = {TU {B}raunschweig} }