Paper accepted for FCCM 2020
Our work titled Comparison of Arithmetic Number Formats for Inference in Sum-Product Networks on FPGAs has been accepted for publication at FCCM2020. The paper investigates the suitability of three different hardware arithmetic formats for the implementation of FPGA-based hardware accelerators for inference in Sum-Product Networks. This work integrates with our previous work on hardware accelerators presented at TPM2018, ICCD2018, FPT2019 and H2RC2019.
Next to researchers from ESA, our former colleague and now professor at HS Fulda, Martin Kumm, contributed to this work. We would also like to thank our colleagues Alejandro Molina and Kristian Kersting from the Machine Learning Lab at TU Darmstadt.
As FCCM will be held as virtual event this year, we will provide a recording of the paper talk in May.
By Lukas Sommer, 27.03.2020
Open PhD Positions
We are currently actively looking to hire a Ph.D. student (Wissenschaftliche/r Mitarbeiter/in) of any gender to do research on extending RISC-V processors. More information is available here
By Prof. Dr-Ing. Andreas Koch, 18.12.2019
Open position for a student assistant (all genders)
The Embedded Systems and Applications Group (ESA) at TU Darmstadt currently has an open position for a student assistant (all genders). ESA is looking for a student who will support the team in a new project by developing Machine Learning (ML) solutions for practically relevant applications as benchmarks for acceleration toolflows on multiple platforms (CPU, GPU, FPGA).
By Lukas Sommer, 17.12.2019
Presentation at H2RC 2019
At the Heterogeneous High-performance Reconfigurable Computing workshop (H2RC 2019), Lukas Sommer presented our paper High-Throughput Multi-Threaded Sum-Product Network Inference in the Reconfigurable Cloud, authored by Micha Ober, Jaco Hofmann, Lukas Sommer, Lukas Weber and Andreas Koch.
In this work, we presented an extension of our TaPaSCo open-source framework to F1 instances available in Amazon’s AWS EC2 cloud. To demonstrate the potential of this platform, we ported our Sum-Product Accelerator to the reconfigurable cloud.
Users interested in using TaPaSCo for AWS EC2 F1 instances can track the status of the integration into mainline TaPaSCo in the TaPaSCo wiki.
By Lukas Sommer, 17.11.2019
Julian Oppermann defends his Ph.D.-thesis
On October 30th, 2019 Julian Oppermann successfully defended his Ph.D.-thesis Advances in ILP-based Modulo Scheduling for High-Level Synthesis. In his work, Julian was able to significantly advance the state-of-the-art in modulo scheduling for High-Level Synthesis.
Congratulations to Dr.-Ing. Julian Oppermann!
By Lukas Sommer, 30.10.2019
Leonardo Solis-Vasquez defends his Ph.D.-thesis
On October 14th, 2019 Leonardo Solis-Vasquez successfully defended his Ph.D.-thesis entitled Accelerating Molecular Docking by Parallelized Heterogeneous Computing - a Case Study of Performance, Quality of Results, and Energy-Efficiency using CPUs, GPUs and FPGAs. In his work, Leonardo contributed accelerated implementations for GPUs and FPGAs to AutoDock, a framework for molecular docking in drug design.
Congratulations to Dr.-Ing. Leonardo Solis-Vasquez!
By Lukas Sommer, 14.10.2019
Two papers accepted for FPT 2019
Two submissions by ESA have been accepted for publication at FPT 2019.
The first paper by Julian Oppermann, Lukas Sommer, Lukas Weber, Melanie Reuter-Oppermann, Andreas Koch and Oliver Sinnen is titled SkyCastle: A Resource-Aware Multi-Loop Scheduler for High-Level Synthesis. In this paper, we developed a resource-aware approach to modulo-scheduling, that integrates allocation and scheduling into a single formulation. This allows to optimize performance by pipelining multiple loops in a kernel while maintaining a given resource allocation.
The second paper by Lukas Weber, Lukas Sommer, Julian Oppermann, Alejandro Molina, Kristian Kersting and Andreas Koch is titled Resource-Efficient Logarithmic Number Scale Arithmetic for SPN Inference on FPGAs. As part of this work, we developed hardware arithmetic operators using the so-called Logarithmic Number System (LNS) for Sum-Product Network inference on FPGAs. In this use-case, the use of LNS allows to save a significant amount of hardware resources while maintaining sufficient accuracy.
By Lukas Sommer, 8.10.2019
Paper accepted for ReConFig 2019
The paper titled A Catalog and In-Hardware Evaluation of Open-Source Drop-In Compatible RISC-V Softcore Processors by Carsten Heinz, Yannick Lavan, Jaco Hofmann and Andreas Koch has been accepted for presentation at ReConFig 2019.
Carsten and his team developed a catalog of open-source RISC-V cores for use with our TaPaSCo framework and conducted an extensive evaluation of these cores on different platforms.
The catalog of RISC-V cores and the wrappers for TaPaSCo are publicly available on Github.
By Lukas Sommer, 30.09.2019
Termin und Raum AER Klausur 2019
Die Klausur findet dieses Mal in Raum S202/C205 statt. Beginn ist am 23.07.2019 um 12 Uhr.
By Dr.-Ing. Jaco Hofmann, 14.07.2019
Paper accepted for EMSoft
As part of the EPHoS-project together with FAT, we have created a collection of benchmark kernels, which allow to assess the performance of different parallel programming models on embedded platforms, such as Nvidia Jetson.
A paper about this benchmark suite has now been accepted for presentation at EMSoft as part of ESWeek 2019 in New York. Together with the paper, we will release our benchmark suite as open-source software on our Github page, so stay tuned!
By Lukas Sommer, 10.07.2019
Report of the EPHoS project available
Throughout the last year, we have been collaborating with the Forschungsvereinigung Automobiltechnik(FAT) to investigate how established parallel programming models from the HPC-domain such as OpenMP, CUDA and OpenCL can be used to parallelize critical workloads in tomorrow’s automotive vehicles.
The report of the project is now available for download as volume 317 of the FAT Schriftenreihe.
By Lukas Sommer, 1.07.2019
TaPaSCo at ISC 2019
Thanks to everyone who stopped by at the booth to learn about how TaPaSCo can help them to build a heterogeneous accelerator SoC for datacenter workloads!
By Lukas Sommer, 17.06.2019
Release of TaPaSCo version 2019.6
In time for ISC-HCP 2019 we have completed the release of TaPaSCo version 2019.6 today!
The release contains a whole lot of new features for the TaPaSCo toolflow and improvements to make bitstream generation faster and more configurable.
Check out the release notes on Github for the full list of new features and improvements.
Also, don’t forget to visit us at booth A-1414 on ISC-HPC on Monday afternoon!
By Lukas Sommer, 14.06.2019
Release of TaPaSCo version 2018.2
We have just completed the release of TaPaSCo version 2018.2! The new release bundles the work of almost one year and contains numerous new features, platforms (Virtex Ultrascale+, Alveo, …) and stability improvements.
Check out the release on Github to find more information about the new features and download TaPaSCo.
By Lukas Sommer, 14.05.2019
Paper accepted for Euro-Par 2019
Our paper titled “Design-Space Exploration with Multi-Objective Resource-Aware Modulo Scheduling” was accepted for publication at Euro-Par.
The paper proposes a new approach for design-space exploration of custom hardware implementations by combining resource allocation and modulo scheduling. Using problem-specific rules, we were able to exclude obviously dominated solutions from the design space before scheduling and synthesis. The evaluation shows the benefits of our approach regarding runtime at the design level when compared to a standard, multi-criteria optimisation method.
By Dr.-Ing. Julian Oppermann, 10.05.2019
PANDAS project kickoff
Today marks the start of the new PANDAS project as part of ESA’s research. The goal of PANDAS (Programmable Appliance for Near-Data processing Accelerated Storage) is to develop a new, smart mass storage card. By combining large numbers of flash memories and programmable logic (FPGAs), critical applications can be accelerated using near-data processing. The resulting PANDAS card is mainly intended for usage with database (e.g. RocksDB) systems, but should be usable with a large variety of applications.
As part of PANDAS, we also welcome Lukas Weber as the newest member of the ESA team. Lukas has previously been with ESA as a student research assistant and during his master thesis.
By Lukas Sommer, 1.05.2019
TaPaSCo article in HiPEAC info 57
HiPEAC info 57 is out and it features an article about our open-source framework TaPaSCo. Check out the article to learn how TaPaSCo can support you when you need to build an FPGA-based heterogeneous system from your accelerator and want to interface it from software.
By Lukas Sommer, 15.04.2019
TaPaSCo tutorial @ ARC 2019
Part of the ARC2019 symposium hosted by ESA was a tutorial about our open-source framework TaPaSCo.
In a combination of short presentations and hands-on sessions, the tutorial covered all necessary steps of the design process for a heterogeneous SoC with TaPaSCo. More than 25 participants of ARC took the opportunity to learn about how the TaPaSCo framework can help them in their every-day research.
The whole tutorial was recorded and we will make a complete video available soon, together with the materials from the tutorial.
By Lukas Sommer, 11.04.2019
ARC 2019 hosted by ESA
From April 9th to April 11th 21019, ESA was host to the 25th edition of the International Symposium on Applied Reconfigurable Computing (ARC).
More than 50 researchers from all over the world gathered in Darmstadt to discuss new architectures and innovative applications for reconfigurable computing. Also part of the conference were two socials events, a guided tour through GSI Helmhotz Zentrum and an interesting visit to ESOC, followed by the conference dinner.
A big thank you to all participants, who made this an interesting conference, and all people involved in the organization of the event!
By Lukas Sommer, 10.04.2019
ESA @ EuroLLVM 2019
The 2019 European LLVM developer’s meeting saw two contributions by students from ESA.
Michael Halkenhäuser successfully participated in the student research competition. As part of the competition, he presented the results of his bachelor thesis, supervised by Lukas Sommer. In this thesis, Michael has developed an alternative OpenMP backend for the polyhedral compilation infrastructure polly, which can act as an drop-in replacement for the existing OpenMP backend. Michael’s new backend was able to achieve significant speedups over the old backend and is now part of the polly project. Take a look at the recording of his talk, to find out more about his work.
Robin Kruppe gave a talk together with Roger Espasa from Esperanto Technologies, presenting details on the RISC-V vector extensions and the current status of support in LLVM. In his job as student assistant at ESA, Robin is doing important work to support code-generation for the RISC-V vector extension as part of the LLVM project. A recording of this talk is also available on YouTube.
By Lukas Sommer, 9.04.2019
Robin Kruppe wins CGO 2019 Student Research Competition
ESA is proud to announce that our student Robin Kruppe has won the gold medal (graduate category) in this year’s CGO student research competition.
In his work titled “Extending LLVM for Lightweight SPMD Vectorization: Using SIMD and Vector Instructions Easily From Any Language”, Robin presented the results of his bachelor thesis, which was supervised by Julian Oppermann. In his thesis, Robin extended the auto-vectorization of LLVM for architectures supporting masked SIMD-instructions (e.g. Nyuzi) and exposed the vectorization interface via LLVM intrinsics.
Congratulations to Robin on this great achievement!
By Lukas Sommer, 20.02.2019