Staff photo for

Research Interests

  • Application Acceleration using FPGA
  • Near Data Processing
  • In-Network Processing
  • FPGA Usability and Toolchains

(Short-)CV

  • seit 2015

    Research Associate at the Embedded Systems and Applications Group (ESA)

  • 2012-2014

    M.Sc. Embedded Systems, TU Delft

  • 2009-2012

    B.Sc. Computer Science, TU Darmstadt

Publications

  1. Krude, J., Hofmann, J., Eichholz, M., Wehrle, K., Koch, A., and Mezini, M. (2019). Online Reprogrammable Multi Tenant Switches. In 1st ACM CoNEXT Workshop on Emerging in-Network Computing Paradigms (CoNEXT ENCP’19). ACM.
    Preprint
    Bibtex
    @inproceedings{krude2019ormts,
      title = {Online Reprogrammable Multi Tenant Switches},
      author = {Krude, Johannes and Hofmann, Jaco and Eichholz, Matthias and Wehrle, Klaus and Koch, Andreas and Mezini, Mira},
      booktitle = {1st ACM CoNEXT Workshop on Emerging in-Network Computing Paradigms (CoNEXT ENCP'19)},
      year = {2019},
      organization = {ACM}
    }
    
  2. Heinz, C., Lavan, Y., Hofmann, J., and Koch, A. (2019). A Catalog and In-Hardware Evaluation of Open-Source Drop-In Compatible RISC-V Softcore Processors. In IEEE Proc. International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE.
    Preprint
    Bibtex
    @inproceedings{heinz2019reconfig,
      title = {A Catalog and In-Hardware Evaluation of Open-Source Drop-In Compatible RISC-V Softcore Processors},
      author = {Heinz, Carsten and Lavan, Yannick and Hofmann, Jaco and Koch, Andreas},
      booktitle = {IEEE Proc. International Conference on ReConFigurable Computing and FPGAs (ReConFig)},
      year = {2019},
      organization = {IEEE}
    }
    
  3. Ober, M., Hofmann, J., Sommer, L., Weber, L., and Koch, A. (2019). High-Throughput Multi-Threaded Sum-Product Network Inference in the Reconfigurable Cloud. In Fifth International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC).
    Preprint
    Bibtex
    @inproceedings{ober2019h2rc,
      title = {High-Throughput Multi-Threaded Sum-Product Network Inference in the Reconfigurable Cloud},
      author = {Ober, Micha and Hofmann, Jaco and Sommer, Lukas and Weber, Lukas and Koch, Andreas},
      booktitle = {Fifth International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)},
      year = {2019}
    }
    
  4. Hofmann, J., Thostrup, L., Ziegler, T., Binnig, C., and Koch, A. (2019). High-Performance In-Network Data Processing. In International Workshop on Accelerating Analytics and Data Management Systems Using Modern Processor and Storage Architectures, ADMS@VLDB 2019, Los Angeles, United States.
    Preprint
    Bibtex
    @inproceedings{adms2019,
      author = {Hofmann, Jaco and Thostrup, Lasse and Ziegler, Tobias and Binnig, Carsten and Koch, Andreas},
      title = {High-Performance In-Network Data Processing},
      booktitle = {International Workshop on Accelerating Analytics and Data Management
                     Systems Using Modern Processor and Storage Architectures, ADMS@VLDB
                     2019, Los Angeles, United States.},
      year = {2019}
    }
    
  5. Korinth, J., Hofmann, J., Heinz, C., and Koch, A. (2019). The TaPaSCo Open-Source Toolflow for the Automated Composition of Task-Based Parallel Reconfigurable Computing Systems. In International Symposium on Applied Reconfigurable Computing (ARC).
    Preprint
    Bibtex
    @inproceedings{korinth2019ttpscostactbprcs,
      title = {The TaPaSCo Open-Source Toolflow for the Automated Composition of Task-Based Parallel Reconfigurable Computing Systems},
      author = {Korinth, Jens and Hofmann, Jaco and Heinz, Carsten and Koch, Andreas},
      booktitle = {International Symposium on Applied Reconfigurable Computing (ARC)},
      year = {2019}
    }
    
  6. Dang, T., Hofmann, J., Liu, Y., Radi, M., Vucinic, D., and Pedone, F. (2018). Consensus for Non-volatile Main Memory. In 2018 IEEE 26th International Conference on Network Protocols (ICNP). IEEE.
    Preprint
    Bibtex
    @inproceedings{dang2018cnmm,
      title = {Consensus for Non-volatile Main Memory},
      author = {Dang, T. and Hofmann, Jaco and Liu, Y. and Radi, M. and Vucinic, D. and Pedone, F.},
      booktitle = {2018 IEEE 26th International Conference on Network Protocols (ICNP)},
      year = {2018},
      organization = {IEEE},
      preprint = {https://ieeexplore.ieee.org/document/8526844}
    }
    
  7. Zjajo, A., Hofmann, J., Christiaanse, J., Eijk, M. van, Smaragdos, G., Strydis, C., Graaf, A. de, et al. (2018). A Real-Time Reconfigurable Multichip Architecture for Large-Scale Biophysically Accurate Neuron Simulation. In IEEE Transactions on Biomedical Circuits and Systems. IEEE.
    Preprint
    Bibtex
    @inproceedings{zjajo2018artrmalsbans,
      title = {A Real-Time Reconfigurable Multichip Architecture for Large-Scale Biophysically Accurate Neuron Simulation},
      author = {Zjajo, A. and Hofmann, Jaco and Christiaanse, J. and van Eijk, M. and Smaragdos, G. and Strydis, C. and de Graaf, A. and Galuzzi, c. and v. Leuken, R.},
      booktitle = {IEEE Transactions on Biomedical Circuits and Systems},
      year = {2018},
      organization = {IEEE},
      preprint = {https://ieeexplore.ieee.org/document/8271870/}
    }
    
  8. Sommer, L., Oppermann, J., Hofmann, J., and Koch, A. (2017). Synthesis of Interleaved Multithreaded Accelerators from OpenMP Loops. In 2017 International Conference on Reconfigurable Computing and FPGAs (ReConFig’17). IEEE.
    Preprint
    Bibtex
    @inproceedings{sommer2017simaompl,
      title = {Synthesis of Interleaved Multithreaded Accelerators from OpenMP Loops},
      author = {Sommer, Lukas and Oppermann, Julian and Hofmann, Jaco and Koch, Andreas},
      booktitle = {2017 International Conference on Reconfigurable Computing and FPGAs (ReConFig'17)},
      year = {2017},
      organization = {IEEE}
    }
    
  9. Hofmann, J., Korinth, J., and Koch, A. (2016). A Scalable Latency-Insensitive Architecture for FPGA-Accelerated Semi-Global Matching in Stereo Vision Applications. In IEEE Proc. International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE.
    Preprint
    Bibtex
    @inproceedings{hofmann2016asliafpgaasgmsva,
      title = {A Scalable Latency-Insensitive Architecture for FPGA-Accelerated Semi-Global Matching in Stereo Vision Applications},
      author = {Hofmann, Jaco and Korinth, Jens and Koch, Andreas},
      booktitle = {IEEE Proc. International Conference on ReConFigurable Computing and FPGAs (ReConFig)},
      year = {2016},
      organization = {IEEE}
    }
    
  10. Hofmann, J., Zjajo, A., and Leuken, R. van. (2016). Multi-chip dataflow architecture for massive scale biophysically accurate neuron simulation. In 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC). IEEE.
    Preprint
    Bibtex
    @inproceedings{hofmann2016m,
      title = {Multi-chip dataflow architecture for massive scale biophysically accurate neuron simulation},
      author = {Hofmann, Jaco and Zjajo, A. and van Leuken, R.},
      booktitle = {38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC)},
      year = {2016},
      organization = {IEEE},
      preprint = {https://ieeexplore.ieee.org/document/7592053/}
    }
    
  11. Hofmann, J., Korinth, J., and Koch, A. (2016). A Scalable High-Performance Hardware Architecture for Real-Time Stereo Vision by Semi-Global Matching. In IEEE Conference on Computer Vision and Pattern Recognition (CVPR) Workshops. IEEE.
    Preprint
    Bibtex
    @inproceedings{hofmann2016ashphartsvsgm,
      title = {A Scalable High-Performance Hardware Architecture for Real-Time Stereo Vision by Semi-Global Matching},
      author = {Hofmann, Jaco and Korinth, Jens and Koch, Andreas},
      booktitle = {IEEE Conference on Computer Vision and Pattern Recognition (CVPR) Workshops},
      year = {2016},
      organization = {IEEE}
    }