Former member

Research Interests

Application Acceleration using FPGA
Near Data Processing
In-Network Processing
FPGA Usability and Toolchains

(Short-)CV

2015-2020

Research Associate at the Embedded Systems and Applications Group (ESA)
2012-2014

M.Sc. Embedded Systems, TU Delft
2009-2012

B.Sc. Computer Science, TU Darmstadt

Publications

Wirth, J., Hofmann, J. A., Thostrup, L., Binnig, C., and Koch, A. (2021). Scalable and Flexible High-Performance In-Network Processing of Hash Joins in Distributed Databases. In International Conference on Field-Programmable Technology (FPT).
Preprint

Bibtex

@inproceedings{wirth2021fpt,
  title = {Scalable and Flexible High-Performance In-Network Processing of Hash Joins in Distributed Databases},
  author = {Wirth, Johannes and Hofmann, Jaco A. and Thostrup, Lasse and Binnig, Carsten and Koch, Andreas},
  booktitle = {International Conference on Field-Programmable Technology (FPT)},
  year = {2021}
}

Wirth, J., Hofmann, J. A., Thostrup, L., Koch, A., and Binnig, C. (2021). Exploiting 3D Memory for Accelerated In-Network Processing of Hash Joins in Distributed Databases. In S. Derrien, F. Hannig, P. C. Diniz, and D. Chillet (Eds.), Applied Reconfigurable Computing. Architectures, Tools, and Applications (pp. 18–32). Cham: Springer International Publishing.
Preprint

Bibtex

@inproceedings{10.1007/978-3-030-79025-7_2,
  author = {Wirth, Johannes and Hofmann, Jaco A. and Thostrup, Lasse and Koch, Andreas and Binnig, Carsten},
  editor = {Derrien, Steven and Hannig, Frank and Diniz, Pedro C. and Chillet, Daniel},
  title = {Exploiting 3D Memory for Accelerated In-Network Processing of Hash Joins in Distributed Databases},
  booktitle = {Applied Reconfigurable Computing. Architectures, Tools, and Applications},
  year = {2021},
  publisher = {Springer International Publishing},
  address = {Cham},
  pages = {18--32},
  isbn = {978-3-030-79025-7}
}

Heinz, C., Hofmann, J., Korinth, J., Sommer, L., Weber, L., and Koch, A. (2021). The TaPaSCo Open-Source Toolflow. Journal of Signal Processing Systems. doi: 10.1007/s11265-021-01640-8
Preprint DOI

Bibtex

@article{heinz2021jsps,
  author = {Heinz, Carsten and Hofmann, Jaco and Korinth, Jens and Sommer, Lukas and Weber, Lukas and Koch, Andreas},
  title = {The TaPaSCo Open-Source Toolflow},
  journal = {Journal of Signal Processing Systems},
  year = {2021},
  month = may,
  day = {02},
  issn = {1939-8115},
  doi = {10.1007/s11265-021-01640-8},
  preprint = {https://link.springer.com/content/pdf/10.1007/s11265-021-01640-8.pdf}
}

Heinz, C., Hofmann, J. A., Sommer, L., and Koch, A. (2020). Improving Job Launch Rates in the TaPaSCo FPGA Middleware by Hardware/Software-Co-Design. In 2020 IEEE/ACM International Workshop on Runtime and Operating Systems for Supercomputers (ROSS) (pp. 22–30). doi: 10.1109/ROSS51935.2020.00008
Preprint DOI

Bibtex

@inproceedings{heinz2020ross,
  author = {{Heinz}, C. and {Hofmann}, J. A. and {Sommer}, L. and {Koch}, A.},
  booktitle = {2020 IEEE/ACM International Workshop on Runtime and Operating Systems for Supercomputers (ROSS)},
  title = {Improving Job Launch Rates in the TaPaSCo FPGA Middleware by Hardware/Software-Co-Design},
  year = {2020},
  volume = {},
  number = {},
  pages = {22-30},
  doi = {10.1109/ROSS51935.2020.00008}
}

Hofmann, J. (2020). An Improved Framework for and Case Studies in FPGA-Based Application Acceleration - Computer Vision, In-Network Processing and Spiking Neural Networks (PhD thesis). Technische Universität Darmstadt, Germany.
Preprint

Bibtex

@phdthesis{hofmann202diss,
  school = {Technische Universität Darmstadt, Germany},
  author = {Hofmann, Jaco},
  title = {An Improved Framework for and Case Studies in FPGA-Based Application Acceleration - Computer Vision, In-Network Processing and Spiking Neural Networks},
  year = {2020},
  preprint = {http://tuprints.ulb.tu-darmstadt.de/10355/}
}

Krude, J., Hofmann, J., Eichholz, M., Wehrle, K., Koch, A., and Mezini, M. (2019). Online Reprogrammable Multi Tenant Switches. In 1st ACM CoNEXT Workshop on Emerging in-Network Computing Paradigms (CoNEXT ENCP’19). ACM.
Preprint

Bibtex

@inproceedings{krude2019ormts,
  title = {Online Reprogrammable Multi Tenant Switches},
  author = {Krude, Johannes and Hofmann, Jaco and Eichholz, Matthias and Wehrle, Klaus and Koch, Andreas and Mezini, Mira},
  booktitle = {1st ACM CoNEXT Workshop on Emerging in-Network Computing Paradigms (CoNEXT ENCP'19)},
  year = {2019},
  organization = {ACM}
}

Heinz, C., Lavan, Y., Hofmann, J., and Koch, A. (2019). A Catalog and In-Hardware Evaluation of Open-Source Drop-In Compatible RISC-V Softcore Processors. In IEEE Proc. International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE. doi: 10.1109/ReConFig48160.2019.8994796
Preprint DOI

Bibtex

@inproceedings{heinz2019reconfig,
  title = {A Catalog and In-Hardware Evaluation of Open-Source Drop-In Compatible RISC-V Softcore Processors},
  author = {Heinz, Carsten and Lavan, Yannick and Hofmann, Jaco and Koch, Andreas},
  booktitle = {IEEE Proc. International Conference on ReConFigurable Computing and FPGAs (ReConFig)},
  year = {2019},
  organization = {IEEE},
  doi = {10.1109/ReConFig48160.2019.8994796}
}

Ober, M., Hofmann, J., Sommer, L., Weber, L., and Koch, A. (2019). High-Throughput Multi-Threaded Sum-Product Network Inference in the Reconfigurable Cloud. In Fifth International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC).
Preprint

Bibtex

@inproceedings{ober2019h2rc,
  title = {High-Throughput Multi-Threaded Sum-Product Network Inference in the Reconfigurable Cloud},
  author = {Ober, Micha and Hofmann, Jaco and Sommer, Lukas and Weber, Lukas and Koch, Andreas},
  booktitle = {Fifth International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)},
  year = {2019}
}

Hofmann, J., Thostrup, L., Ziegler, T., Binnig, C., and Koch, A. (2019). High-Performance In-Network Data Processing. In International Workshop on Accelerating Analytics and Data Management Systems Using Modern Processor and Storage Architectures, ADMS@VLDB 2019, Los Angeles, United States.
Preprint

Bibtex

@inproceedings{adms2019,
  author = {Hofmann, Jaco and Thostrup, Lasse and Ziegler, Tobias and Binnig, Carsten and Koch, Andreas},
  title = {High-Performance In-Network Data Processing},
  booktitle = {International Workshop on Accelerating Analytics and Data Management
                 Systems Using Modern Processor and Storage Architectures, ADMS@VLDB
                 2019, Los Angeles, United States.},
  year = {2019}
}

Korinth, J., Hofmann, J., Heinz, C., and Koch, A. (2019). The TaPaSCo Open-Source Toolflow for the Automated Composition of Task-Based Parallel Reconfigurable Computing Systems. In International Symposium on Applied Reconfigurable Computing (ARC). doi: 10.1007/978-3-030-17227-5_16
Preprint DOI

Bibtex

@inproceedings{korinth2019ttpscostactbprcs,
  title = {The TaPaSCo Open-Source Toolflow for the Automated Composition of Task-Based Parallel Reconfigurable Computing Systems},
  author = {Korinth, Jens and Hofmann, Jaco and Heinz, Carsten and Koch, Andreas},
  booktitle = {International Symposium on Applied Reconfigurable Computing (ARC)},
  year = {2019},
  doi = {10.1007/978-3-030-17227-5_16}
}

Dang, T., Hofmann, J., Liu, Y., Radi, M., Vucinic, D., and Pedone, F. (2018). Consensus for Non-volatile Main Memory. In 2018 IEEE 26th International Conference on Network Protocols (ICNP). IEEE.
Preprint

Bibtex

@inproceedings{dang2018cnmm,
  title = {Consensus for Non-volatile Main Memory},
  author = {Dang, T. and Hofmann, Jaco and Liu, Y. and Radi, M. and Vucinic, D. and Pedone, F.},
  booktitle = {2018 IEEE 26th International Conference on Network Protocols (ICNP)},
  year = {2018},
  organization = {IEEE},
  preprint = {https://ieeexplore.ieee.org/document/8526844}
}

Zjajo, A., Hofmann, J., Christiaanse, J., Eijk, M. van, Smaragdos, G., Strydis, C., Graaf, A. de, et al. (2018). A Real-Time Reconfigurable Multichip Architecture for Large-Scale Biophysically Accurate Neuron Simulation. In IEEE Transactions on Biomedical Circuits and Systems. IEEE.
Preprint

Bibtex

@inproceedings{zjajo2018artrmalsbans,
  title = {A Real-Time Reconfigurable Multichip Architecture for Large-Scale Biophysically Accurate Neuron Simulation},
  author = {Zjajo, A. and Hofmann, Jaco and Christiaanse, J. and van Eijk, M. and Smaragdos, G. and Strydis, C. and de Graaf, A. and Galuzzi, c. and v. Leuken, R.},
  booktitle = {IEEE Transactions on Biomedical Circuits and Systems},
  year = {2018},
  organization = {IEEE},
  preprint = {https://ieeexplore.ieee.org/document/8271870/}
}

Sommer, L., Oppermann, J., Hofmann, J., and Koch, A. (2017). Synthesis of Interleaved Multithreaded Accelerators from OpenMP Loops. In 2017 International Conference on Reconfigurable Computing and FPGAs (ReConFig’17). IEEE.
Preprint

Bibtex

@inproceedings{sommer2017simaompl,
  title = {Synthesis of Interleaved Multithreaded Accelerators from OpenMP Loops},
  author = {Sommer, Lukas and Oppermann, Julian and Hofmann, Jaco and Koch, Andreas},
  booktitle = {2017 International Conference on Reconfigurable Computing and FPGAs (ReConFig'17)},
  year = {2017},
  organization = {IEEE}
}

Hofmann, J., Korinth, J., and Koch, A. (2016). A Scalable Latency-Insensitive Architecture for FPGA-Accelerated Semi-Global Matching in Stereo Vision Applications. In IEEE Proc. International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE.
Preprint

Bibtex

@inproceedings{hofmann2016asliafpgaasgmsva,
  title = {A Scalable Latency-Insensitive Architecture for FPGA-Accelerated Semi-Global Matching in Stereo Vision Applications},
  author = {Hofmann, Jaco and Korinth, Jens and Koch, Andreas},
  booktitle = {IEEE Proc. International Conference on ReConFigurable Computing and FPGAs (ReConFig)},
  year = {2016},
  organization = {IEEE}
}

Hofmann, J., Zjajo, A., and Leuken, R. van. (2016). Multi-chip dataflow architecture for massive scale biophysically accurate neuron simulation. In 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC). IEEE.
Preprint

Bibtex

@inproceedings{hofmann2016m,
  title = {Multi-chip dataflow architecture for massive scale biophysically accurate neuron simulation},
  author = {Hofmann, Jaco and Zjajo, A. and van Leuken, R.},
  booktitle = {38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC)},
  year = {2016},
  organization = {IEEE},
  preprint = {https://ieeexplore.ieee.org/document/7592053/}
}

Hofmann, J., Korinth, J., and Koch, A. (2016). A Scalable High-Performance Hardware Architecture for Real-Time Stereo Vision by Semi-Global Matching. In IEEE Conference on Computer Vision and Pattern Recognition (CVPR) Workshops. IEEE.
Best-Paper Runner-Up Preprint

Bibtex

@inproceedings{hofmann2016ashphartsvsgm,
  title = {A Scalable High-Performance Hardware Architecture for Real-Time Stereo Vision by Semi-Global Matching},
  author = {Hofmann, Jaco and Korinth, Jens and Koch, Andreas},
  booktitle = {IEEE Conference on Computer Vision and Pattern Recognition (CVPR) Workshops},
  year = {2016},
  organization = {IEEE}
}