Staff photo for

Research Interests

  • Application Acceleration using FPGA
  • Near Data Processing
  • In-Network Processing
  • FPGA Usability and Toolchains

(Short-)CV

  • seit 2015

    Research Associate at the Embedded Systems and Applications Group (ESA)

  • 2012-2014

    M.Sc. Embedded Systems, TU Delft

  • 2009-2012

    B.Sc. Computer Science, TU Darmstadt

Publications

  1. Hofmann, J., Thostrup, L., Ziegler, T., Binnig, C., and Koch, A. (2019). High-Performance In-Network Data Processing. In International Workshop on Accelerating Analytics and Data Management Systems Using Modern Processor and Storage Architectures, ADMS@VLDB 2019, Los Angeles, United States.
    Bibtex
    @inproceedings{adms2019,
      author = {Hofmann, Jaco and Thostrup, Lasse and Ziegler, Tobias and Binnig, Carsten and Koch, Andreas},
      title = {High-Performance In-Network Data Processing},
      booktitle = {International Workshop on Accelerating Analytics and Data Management
                     Systems Using Modern Processor and Storage Architectures, ADMS@VLDB
                     2019, Los Angeles, United States.},
      year = {2019}
    }
    
  2. Korinth, J., Hofmann, J., Heinz, C., and Koch, A. (2019). The TaPaSCo Open-Source Toolflow for the Automated Composition of Task-Based Parallel Reconfigurable Computing Systems. In International Symposium on Applied Reconfigurable Computing (ARC).
    Preprint
    Bibtex
    @inproceedings{korinth2019ttpscostactbprcs,
      title = {The TaPaSCo Open-Source Toolflow for the Automated Composition of Task-Based Parallel Reconfigurable Computing Systems},
      author = {Korinth, Jens and Hofmann, Jaco and Heinz, Carsten and Koch, Andreas},
      booktitle = {International Symposium on Applied Reconfigurable Computing (ARC)},
      year = {2019}
    }
    
  3. Dang, T., Hofmann, J., Liu, Y., Radi, M., Vucinic, D., and Pedone, F. (2018). Consensus for Non-volatile Main Memory. In 2018 IEEE 26th International Conference on Network Protocols (ICNP).
    Preprint
    Bibtex
    @inproceedings{dang2018cnmm,
      title = {Consensus for Non-volatile Main Memory},
      author = {Dang, T. and Hofmann, Jaco and Liu, Y. and Radi, M. and Vucinic, D. and Pedone, F.},
      booktitle = {2018 IEEE 26th International Conference on Network Protocols (ICNP)},
      year = {2018},
      organizazion = {IEEE},
      preprint = {https://ieeexplore.ieee.org/document/8526844}
    }
    
  4. Zjajo, A., Hofmann, J., Christiaanse, J., Eijk, M. van, Smaragdos, G., Strydis, C., Graaf, A. de, et al. (2018). A Real-Time Reconfigurable Multichip Architecture for Large-Scale Biophysically Accurate Neuron Simulation. In IEEE Transactions on Biomedical Circuits and Systems.
    Preprint
    Bibtex
    @inproceedings{zjajo2018artrmalsbans,
      title = {A Real-Time Reconfigurable Multichip Architecture for Large-Scale Biophysically Accurate Neuron Simulation},
      author = {Zjajo, A. and Hofmann, Jaco and Christiaanse, J. and van Eijk, M. and Smaragdos, G. and Strydis, C. and de Graaf, A. and Galuzzi, c. and v. Leuken, R.},
      booktitle = {IEEE Transactions on Biomedical Circuits and Systems},
      year = {2018},
      organizazion = {IEEE},
      preprint = {https://ieeexplore.ieee.org/document/8271870/}
    }
    
  5. Sommer, L., Oppermann, J., Hofmann, J., and Koch, A. (2017). Synthesis of Interleaved Multithreaded Accelerators from OpenMP Loops. In 2017 International Conference on Reconfigurable Computing and FPGAs (ReConFig’17).
    Preprint
    Bibtex
    @inproceedings{sommer2017simaompl,
      title = {Synthesis of Interleaved Multithreaded Accelerators from OpenMP Loops},
      author = {Sommer, Lukas and Oppermann, Julian and Hofmann, Jaco and Koch, Andreas},
      booktitle = {2017 International Conference on Reconfigurable Computing and FPGAs (ReConFig'17)},
      year = {2017},
      organizazion = {IEEE}
    }
    
  6. Hofmann, J., Korinth, J., and Koch, A. (2016). A Scalable Latency-Insensitive Architecture for FPGA-Accelerated Semi-Global Matching in Stereo Vision Applications. In IEEE Proc. International Conference on ReConFigurable Computing and FPGAs (ReConFig).
    Preprint
    Bibtex
    @inproceedings{hofmann2016asliafpgaasgmsva,
      title = {A Scalable Latency-Insensitive Architecture for FPGA-Accelerated Semi-Global Matching in Stereo Vision Applications},
      author = {Hofmann, Jaco and Korinth, Jens and Koch, Andreas},
      booktitle = {IEEE Proc. International Conference on ReConFigurable Computing and FPGAs (ReConFig)},
      year = {2016},
      organizazion = {IEEE}
    }
    
  7. Hofmann, J., Zjajo, A., and Leuken, R. van. (2016). Multi-chip dataflow architecture for massive scale biophysically accurate neuron simulation. In 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC).
    Preprint
    Bibtex
    @inproceedings{hofmann2016m,
      title = {Multi-chip dataflow architecture for massive scale biophysically accurate neuron simulation},
      author = {Hofmann, Jaco and Zjajo, A. and van Leuken, R.},
      booktitle = {38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC)},
      year = {2016},
      organizazion = {IEEE},
      preprint = {https://ieeexplore.ieee.org/document/7592053/}
    }
    
  8. Hofmann, J., Korinth, J., and Koch, A. (2016). A Scalable High-Performance Hardware Architecture for Real-Time Stereo Vision by Semi-Global Matching. In IEEE Conference on Computer Vision and Pattern Recognition (CVPR) Workshops.
    Preprint
    Bibtex
    @inproceedings{hofmann2016ashphartsvsgm,
      title = {A Scalable High-Performance Hardware Architecture for Real-Time Stereo Vision by Semi-Global Matching},
      author = {Hofmann, Jaco and Korinth, Jens and Koch, Andreas},
      booktitle = {IEEE Conference on Computer Vision and Pattern Recognition (CVPR) Workshops},
      year = {2016},
      organizazion = {IEEE}
    }