• Technische Universität Darmstadt
• Computer Science Department (FB20)
• Embedded Systems & Applications Group (ESA)


• Former member

Profiles

• Google Scholar
• ResearchGate
• DBLP

Publications

1. Weckert, C., Solis-Vasquez, L., Oppermann, J., Koch, A., and Sinnen, O. (2023). Altis-SYCL: Migrating Altis Benchmarking Suite from CUDA to SYCL for GPUs and FPGAs. In Proceedings of the SC ’23 Workshops of The International Conference on High Performance Computing, Network, Storage, and Analysis. Association for Computing Machinery. doi: 10.1145/3624062.3624542
   Preprint DOI Slides
   Bibtex

   @inproceedings{weckert2023h2rc,
     author = {Weckert, Christoph and Solis-Vasquez, Leonardo and Oppermann, Julian and Koch, Andreas and Sinnen, Oliver},
     title = {Altis-SYCL: Migrating Altis Benchmarking Suite from CUDA to SYCL for GPUs and FPGAs},
     booktitle = {Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, Network, Storage, and Analysis},
     year = {2023},
     publisher = {Association for Computing Machinery},
     doi = {10.1145/3624062.3624542}
   }
   

2. Oppermann, J., Mickaliger, M. B., and Sinnen, O. (2023). Pulsar search acceleration using FPGAs and OpenCL templates. Experimental Astronomy. doi: 10.1007/s10686-022-09888-z
   DOI
   Bibtex

   @article{jo2023expa,
     title = {Pulsar search acceleration using {FPGAs} and {OpenCL} templates},
     issn = {1572-9508},
     doi = {10.1007/s10686-022-09888-z},
     journal = {Experimental Astronomy},
     author = {Oppermann, Julian and Mickaliger, Mitchell B. and Sinnen, Oliver},
     year = {2023}
   }
   

3. Oppermann, J., Urbach, M., and Demme, J. (2022). How to Make Hardware with Maths: An Introduction to CIRCT’s Scheduling Infrastructure. In 2022 European LLVM Developers’ Meeting (EuroLLVM).
   Slides Video
   Bibtex

   @inproceedings{oppermann2022eurollvm,
     author = {Oppermann, Julian and Urbach, Mike and Demme, John},
     title = {How to {Make} {Hardware} with {Maths}: {An} {Introduction} to {CIRCT}'s {Scheduling} {Infrastructure}},
     booktitle = {2022 European {LLVM} {Developers}' {Meeting} ({EuroLLVM})},
     year = {2022},
     video = {https://youtu.be/tctEk7O5DU0}
   }
   

4. Damian, M., Oppermann, J., Spang, C., and Koch, A. (2022). SCAIE-V: An Open-Source SCAlable Interface for ISA Extensions for RISC-V Processors. In 2022 The 59th Design Automation Conference (DAC). doi: 10.1145/3489517.3530432
   HiPEAC Award Preprint DOI URL
   Bibtex

   @inproceedings{damian2022dac,
     title = {SCAIE-V: An Open-Source SCAlable Interface for ISA Extensions for RISC-V Processors},
     author = {Damian, Mihaela and Oppermann, Julian and Spang, Christoph and Koch, Andreas},
     booktitle = {2022 The 59th Design Automation Conference (DAC)},
     year = {2022},
     url = {https://doi.org/10.1145/3489517.3530432},
     doi = {10.1145/3489517.3530432}
   }
   

5. Ecker, W., Adelt, P., Müller, W., Heckmann, R., Krstic, M., Herdt, V., Drechsler, R., et al. (2022). The Scale4Edge RISC-V Ecosystem. In 2022 Design, Automation & Test in Europe Conference (DATE). doi: 10.23919/DATE54114.2022.9774593
   Preprint DOI
   Bibtex

   @inproceedings{s4e2022date,
     author = {Ecker, Wolfgang and Adelt, Peer and M{\"{u}}ller, Wolfgang and Heckmann, Reinhold and Krstic, Milos and Herdt, Vladimir and Drechsler, Rolf and Angst, Gerhard and Wimmer, Ralf and Mauderer, Andreas and Stahl, Rafael and Emrich, Karsten and Mueller{-}Gritschneder, Daniel and Becker, Bernd and Scholl, Philipp and Jentzsch, Eyck and Schlamelcher, Jan and Gr{\"{u}}ttner, Kim and Bernardo, Paul Palomero and Bringmann, Oliver and Damian, Mihaela and Oppermann, Julian and Koch, Andreas and Bormann, J{\"{o}}rg and Partzsch, Johannes and Mayr, Christian and Kunz, Wolfgang},
     title = {The Scale4Edge {RISC-V} Ecosystem},
     booktitle = {2022 Design, Automation {\&} Test in Europe Conference ({DATE})},
     year = {2022},
     doi = {10.23919/DATE54114.2022.9774593}
   }
   

6. Oppermann, J., Reuter-Oppermann, M., Koch, A., and Sinnen, O. (2022). "Optimising" High-level Synthesis in CIRCT. In 2nd Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE’22).
   Preprint Video
   Bibtex

   @inproceedings{oppermann2022latte,
     title = {"Optimising" High-level Synthesis in CIRCT},
     author = {Oppermann, Julian and Reuter-Oppermann, Melanie and Koch, Andreas and Sinnen, Oliver},
     booktitle = {2nd Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE'22)},
     year = {2022},
     video = {https://youtu.be/7qMdPTLt12c}
   }
   

7. Kruppe, H., Sommer, L., Weber, L., Oppermann, J., Axenie, C., and Koch, A. (2021). Efficient Operator Sharing Modulo Scheduling for Sum-Product Network Inference on FPGAs. In Intl. Conf. on Embedded Computer Systems: Architectures, MOdeling and Simulation (SAMOS). Springer International Publishing.
   Preprint
   Bibtex

   @inproceedings{kruppe2021samos,
     title = {Efficient Operator Sharing Modulo Scheduling for Sum-Product Network Inference on FPGAs},
     author = {Kruppe, Hanna and Sommer, Lukas and Weber, Lukas and Oppermann, Julian and Axenie, Cristian and Koch, Andreas},
     booktitle = {Intl. Conf. on Embedded Computer Systems: Architectures, MOdeling and Simulation (SAMOS)},
     year = {2021},
     publisher = {Springer International Publishing}
   }
   

8. Oppermann, J. (2019). Advances in ILP-based Modulo Scheduling for High-Level Synthesis (PhD thesis). Technische Universität Darmstadt, Germany.
   Preprint
   Bibtex

   @phdthesis{oppermann2019diss,
     author = {Oppermann, Julian},
     title = {Advances in ILP-based Modulo Scheduling for High-Level Synthesis},
     school = {Technische Universität Darmstadt, Germany},
     year = {2019},
     preprint = {https://tuprints.ulb.tu-darmstadt.de/9272/}
   }
   

9. Weber, L., Sommer, L., Oppermann, J., Molina, A., Kersting, K., and Koch, A. (2019). Resource-Efficient Logarithmic Number Scale Arithmetic for SPN Inference on FPGAs. In International Conference on Field-Programmable Technology (FPT).
   Preprint Slides Poster
   Bibtex

   @inproceedings{weber2019relnsafsiof,
     title = {Resource-Efficient Logarithmic Number Scale Arithmetic for SPN Inference on FPGAs},
     author = {Weber, Lukas and Sommer, Lukas and Oppermann, Julian and Molina, Alejandro and Kersting, Kristian and Koch, Andreas},
     booktitle = {International Conference on Field-Programmable Technology (FPT)},
     year = {2019}
   }
   

10. Oppermann, J., Sommer, L., Weber, L., Reuter-Oppermann, M., Koch, A., and Sinnen, O. (2019). SkyCastle: A Resource-Aware Multi-Loop Scheduler for High-Level Synthesis. In International Conference on Field-Programmable Technology (FPT).
    Preprint Slides
    Bibtex

    @inproceedings{oppermann2019scamlsfhls,
      title = {SkyCastle: A Resource-Aware Multi-Loop Scheduler for High-Level Synthesis},
      author = {Oppermann, Julian and Sommer, Lukas and Weber, Lukas and Reuter-Oppermann, Melanie and Koch, Andreas and Sinnen, Oliver},
      booktitle = {International Conference on Field-Programmable Technology (FPT)},
      year = {2019}
    }
    

11. Oppermann, J., Sittel, P., Kumm, M., Reuter-Oppermann, M., Koch, A., and Sinnen, O. (2019). Design-Space Exploration with Multi-Objective Resource-Aware Modulo Scheduling. In International European Conference on Parallel and Distributed Computing (Euro-Par), Göttingen, Germany.
    Preprint Slides
    Bibtex

    @inproceedings{oppermann2019dsemorams,
      author = {Oppermann, Julian and Sittel, Patrick and Kumm, Martin and Reuter{-}Oppermann, Melanie and Koch, Andreas and Sinnen, Oliver},
      title = {{Design-Space Exploration with Multi-Objective Resource-Aware Modulo Scheduling}},
      booktitle = {International European Conference on Parallel and Distributed Computing (Euro-Par), Göttingen, Germany},
      year = {2019}
    }
    

12. Oppermann, J., Reuter-Oppermann, M., Sommer, L., Koch, A., and Sinnen, O. (2019). Exact and Practical Modulo Scheduling for High-Level Synthesis. TRETS, 12(2), 8:1–8:26. doi: 10.1145/3317670
    Preprint DOI
    Bibtex

    @article{oppermann2019epmshs,
      author = {Oppermann, Julian and Reuter{-}Oppermann, Melanie and Sommer, Lukas and Koch, Andreas and Sinnen, Oliver},
      title = {Exact and Practical Modulo Scheduling for High-Level Synthesis},
      journal = {{TRETS}},
      volume = {12},
      number = {2},
      pages = {8:1--8:26},
      year = {2019},
      doi = {10.1145/3317670}
    }
    

13. Kruppe, R., Oppermann, J., Sommer, L., and Koch, A. (2019). Extending LLVM for Lightweight SPMD Vectorization: Using SIMD and Vector Instructions Easily from Any Language . In 2019 International Symposium on Code Generation and Optimization.
    Preprint
    Bibtex

    @inproceedings{kruppe2019ellvmlspmdvusimdvieal,
      title = {Extending LLVM for Lightweight SPMD Vectorization: Using SIMD and Vector Instructions Easily from Any Language },
      author = {Kruppe, Robin and Oppermann, Julian and Sommer, Lukas and Koch, Andreas},
      booktitle = {2019 International Symposium on Code Generation and Optimization},
      year = {2019}
    }
    

14. Oppermann, J., Sommer, L., and Koch, A. (2019). SpExSim: assessing kernel suitability for C-based high-level hardware synthesis. In Journal of Supercomputing.
    Preprint The original publication is available at www.springerlink.com
    Bibtex

    @inproceedings{oppermann2019sesc,
      title = {SpExSim: assessing kernel suitability for C-based high-level hardware synthesis},
      author = {Oppermann, Julian and Sommer, Lukas and Koch, Andreas},
      booktitle = {Journal of Supercomputing},
      year = {2019},
      springer = {http://link.springer.com/article/10.1007/s11227-017-2101-z}
    }
    

15. Sommer, L., Oppermann, J., Molina, A., Binnig, C., Kersting, K., and Koch, A. (2018). Automatic Mapping of the Sum-Product Network Inference Problem to FPGA-based Accelerators. In IEEE International Conference on Computer Design (ICCD). IEEE.
    Preprint
    Bibtex

    @inproceedings{sommer2018amspnipfpgaa,
      title = {Automatic Mapping of the Sum-Product Network Inference Problem to FPGA-based Accelerators},
      author = {Sommer, Lukas and Oppermann, Julian and Molina, Alejandro and Binnig, Carsten and Kersting, Kristian and Koch, Andreas},
      booktitle = {IEEE International Conference on Computer Design (ICCD)},
      year = {2018},
      organization = {IEEE}
    }
    

16. Oppermann, J., Vollbrecht, S., Reuter-Oppermann, M., Sinnen, O., and Koch, A. (2018). Work in Progress: GeMS: A Generator for Modulo Scheduling Problems. In Intl. Conf. on Compilers, Architectures and Synthesis For Embedded Systems (CASES).
    Preprint Slides Poster
    Bibtex

    @inproceedings{oppermann2018wpgmsagmsp,
      title = {Work in Progress: GeMS: A Generator for Modulo Scheduling Problems},
      author = {Oppermann, Julian and Vollbrecht, Sebastian and Reuter-Oppermann, Melanie and Sinnen, Oliver and Koch, Andreas},
      booktitle = {Intl. Conf. on Compilers,  Architectures and Synthesis For Embedded Systems (CASES)},
      year = {2018}
    }
    

17. Oppermann, J., Reuter-Oppermann, M., Sommer, L., Sinnen, O., and Koch, A. (2018). Dependence Graph Preprocessing for Faster Exact Modulo Scheduling in High-level Synthesis. In Intl. Conf. on Field Programmable Logic and Applications (FPL).
    Preprint Slides
    Bibtex

    @inproceedings{oppermann2018dgpfemshs,
      title = {Dependence Graph Preprocessing for Faster Exact Modulo Scheduling in High-level Synthesis},
      author = {Oppermann, Julian and Reuter-Oppermann, Melanie and Sommer, Lukas and Sinnen, Oliver and Koch, Andreas},
      booktitle = {Intl. Conf. on Field Programmable Logic and Applications (FPL)},
      year = {2018}
    }
    

18. Sittel, P., Kumm, M., Oppermann, J., Möller, K., Zipf, P., and Koch, A. (2018). ILP-based Modulo Scheduling and Binding for Register Minimization. In Intl. Conf. on Field Programmable Logic and Applications (FPL).
    Preprint
    Bibtex

    @inproceedings{sittel2018ilpmsbrm,
      title = {ILP-based Modulo Scheduling and Binding for Register Minimization},
      author = {Sittel, Patrick and Kumm, Martin and Oppermann, Julian and Möller, Konrad and Zipf, Peter and Koch, Andreas},
      booktitle = {Intl. Conf. on Field Programmable Logic and Applications (FPL)},
      year = {2018}
    }
    

19. Sittel, P., Oppermann, J., Kumm, M., Koch, A., and Zipf, P. (2018). HatScheT: A Contribution to Agile HLS. In FPGAs for Software Programmers (FSP).
    Preprint
    Bibtex

    @inproceedings{sittel2018hstacahls,
      title = {HatScheT: A Contribution to Agile HLS},
      author = {Sittel, Patrick and Oppermann, Julian and Kumm, Martin and Koch, Andreas and Zipf, Peter},
      booktitle = {FPGAs for Software Programmers (FSP)},
      year = {2018}
    }
    

20. Sommer, L., Oppermann, J., Molina, A., Binnig, C., Kersting, K., and Koch, A. (2018). Automatic Synthesis of FPGA-based Accelerators for the Sum-Product Network Inference Problem. In ICML 2018 Workshop on Tractable Probabilistic Models (TPM). ICML.
    Preprint
    Bibtex

    @inproceedings{sommer2018asfpgaaspnip,
      title = {Automatic Synthesis of FPGA-based Accelerators for the Sum-Product Network Inference Problem},
      author = {Sommer, Lukas and Oppermann, Julian and Molina, Alejandro and Binnig, Carsten and Kersting, Kristian and Koch, Andreas},
      booktitle = {ICML 2018 Workshop on Tractable Probabilistic Models (TPM)},
      year = {2018},
      organization = {ICML}
    }
    

21. Kruppe, R., Oppermann, J., and Koch, A. (2018). Supporting the RISC-V Vector Extensions in LLVM. In 2018 European LLVM Developers Meeting.
    Slides Video Material
    Bibtex

    @inproceedings{kruppe2018sriscvvellvm,
      title = {Supporting the RISC-V Vector Extensions in LLVM},
      author = {Kruppe, Robin and Oppermann, Julian and Koch, Andreas},
      booktitle = {2018 European LLVM Developers Meeting},
      year = {2018},
      video = {https://youtu.be/iSMLYHRlNVc},
      slides = {http://llvm.org/devmtg/2018-04/slides/Kruppe-Supporting%20the%20Risc-V%20vector%20ext.pdf},
      material = {https://llvm.org/devmtg/2018-04/talks.html#Lightning_18}
    }
    

22. Sommer, L., Oppermann, J., Korinth, J., and Koch, A. (2018). Offloading OpenMP Target Regions to FPGA Accelerators Using LLVM. In 2018 European LLVM Developers Meeting.
    Preprint
    Bibtex

    @inproceedings{sommer2018oomptrfpgaaullvm,
      title = {Offloading OpenMP Target Regions to FPGA Accelerators Using LLVM},
      author = {Sommer, Lukas and Oppermann, Julian and Korinth, Jens and Koch, Andreas},
      booktitle = {2018 European LLVM Developers Meeting},
      year = {2018}
    }
    

23. Vincon, T., Haddock, S., Riegger, C., Oppermann, J., Koch, A., and Petrov, I. (2018). NoFTL-KV: Tackling Write-Amplification on KV-Stores with Native Storage Management. In Proc. of the 21st International Conference on Extending Database Technology (EDBT).
    Preprint
    Bibtex

    @inproceedings{vincon2018nftlkvtwakvsnsm,
      title = {NoFTL-KV: Tackling Write-Amplification on KV-Stores with Native Storage Management},
      author = {Vincon, Tobias and Haddock, Sergey and Riegger, Christian and Oppermann, Julian and Koch, Andreas and Petrov, Ilia},
      booktitle = {Proc. of the 21st International Conference on Extending Database Technology (EDBT)},
      year = {2018}
    }
    

24. Liebig, B., Oppermann, J., Sinnen, O., and Koch, A. (2018). Improved High-Level Synthesis for Complex CellML Models. In Proc. 14th International Symposium on Applied Reconfigurable Computing (ARC).
    Preprint
    Bibtex

    @inproceedings{liebig2018ihlsccmlm,
      title = {Improved High-Level Synthesis for Complex CellML Models},
      author = {Liebig, Björn and Oppermann, Julian and Sinnen, Oliver and Koch, Andreas},
      booktitle = {Proc. 14th International Symposium on Applied Reconfigurable Computing (ARC)},
      year = {2018}
    }
    

25. Sommer, L., Oppermann, J., Hofmann, J., and Koch, A. (2017). Synthesis of Interleaved Multithreaded Accelerators from OpenMP Loops. In 2017 International Conference on Reconfigurable Computing and FPGAs (ReConFig’17). IEEE.
    Preprint
    Bibtex

    @inproceedings{sommer2017simaompl,
      title = {Synthesis of Interleaved Multithreaded Accelerators from OpenMP Loops},
      author = {Sommer, Lukas and Oppermann, Julian and Hofmann, Jaco and Koch, Andreas},
      booktitle = {2017 International Conference on Reconfigurable Computing and FPGAs (ReConFig'17)},
      year = {2017},
      organization = {IEEE}
    }
    

26. Sommer, L., Oppermann, J., and Koch, A. (2016). C-based Synthesis of Area-Efficient Accelerators for OpenMP Worksharing Loops. In Second International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC).
    Preprint
    Bibtex

    @inproceedings{sommer2016csaeaompwl,
      title = {C-based Synthesis of Area-Efficient Accelerators for OpenMP Worksharing Loops},
      author = {Sommer, Lukas and Oppermann, Julian and Koch, Andreas},
      booktitle = {Second International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)},
      year = {2016}
    }
    

27. Oppermann, J., Koch, A., Reuter-Oppermann, M., and Sinnen, O. (2016). ILP-based Modulo Scheduling for High-level Synthesis. In International Conference on Compilers, Architectures and Synthesis For Embedded Systems (CASES).
    Preprint Slides Poster Material
    Bibtex

    @inproceedings{oppermann2016ilpmshs,
      title = {ILP-based Modulo Scheduling for High-level Synthesis},
      author = {Oppermann, Julian and Koch, Andreas and Reuter-Oppermann, Melanie and Sinnen, Oliver},
      booktitle = {International Conference on Compilers, Architectures and Synthesis For Embedded Systems (CASES)},
      year = {2016},
      material = {http://dx.doi.org/10.1145/2968455.2968512}
    }
    

28. Oppermann, J., and Koch, A. (2016). Detecting Kernels Suitable for C-based High-Level Hardware Synthesis. In 2nd International Workshop on Reengineering for Parallelism in Heterogeneous Parallel Platforms (RePara).
    Preprint
    Bibtex

    @inproceedings{oppermann2016dkschlhs,
      title = {Detecting Kernels Suitable for C-based High-Level Hardware Synthesis},
      author = {Oppermann, Julian and Koch, Andreas},
      booktitle = {2nd International Workshop on Reengineering for Parallelism in Heterogeneous Parallel Platforms (RePara)},
      year = {2016}
    }
    

29. Oppermann, J., Koch, A., Yu, T., and Sinnen, O. (2015). Domain-specific Optimisation for the High-level Synthesis of CellML-based Simulation Accelerators. In IEEE Proc. Intl. Conf. on Field Programmable Logic and Applications (FPL). IEEE.
    Preprint Slides
    Bibtex

    @inproceedings{oppermann2015dohscmlsa,
      title = {Domain-specific Optimisation for the High-level Synthesis of CellML-based Simulation Accelerators},
      author = {Oppermann, Julian and Koch, Andreas and Yu, Ting and Sinnen, Oliver},
      booktitle = {IEEE Proc.  Intl. Conf. on Field Programmable Logic and Applications (FPL)},
      year = {2015},
      organization = {IEEE}
    }
    

30. Yu, T., Oppermann, J., Bradley, C., and Sinnen, O. (2015). Performance optimisation strategies for automatically generated FPGA accelerators for biomedical models. In Concurrency and Computation: Practice and Experience.
    Preprint
    Bibtex

    @inproceedings{yu2015pfpga,
      title = {Performance optimisation strategies for automatically generated FPGA accelerators for biomedical models},
      author = {Yu, Ting and Oppermann, Julian and Bradley, Chris and Sinnen, Oliver},
      booktitle = {Concurrency and Computation: Practice and Experience},
      year = {2015},
      preprint = {http://dx.doi.org/10.1002/cpe.3699}
    }
    

31. Huthmann, J., Oppermann, J., and Koch, A. (2014). Automatic high-level synthesis of multi-threaded hardware accelerators. In IEEE Proc. Intl. Conf. on Field Programmable Logic and Applications (FPL). IEEE.
    Preprint
    Bibtex

    @inproceedings{huthmann2014a,
      title = {Automatic high-level synthesis of multi-threaded hardware accelerators},
      author = {Huthmann, Jens and Oppermann, Julian and Koch, Andreas},
      booktitle = {IEEE Proc.  Intl. Conf. on Field Programmable Logic and Applications (FPL)},
      year = {2014},
      organization = {IEEE}
    }
    

32. Huthmann, J., Liebig, B., Oppermann, J., and Koch, A. (2013). Hardware/software co-compilation with the Nymble system. In Proc. of the Intl. Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC).
    Preprint
    Bibtex

    @inproceedings{huthmann2013hscc,
      title = {Hardware/software co-compilation with the Nymble system},
      author = {Huthmann, Jens and Liebig, Björn and Oppermann, Julian and Koch, Andreas},
      booktitle = {Proc. of the Intl. Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)},
      year = {2013}
    }