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Forschungsgebiete

  • Hardware-Beschleuniger
  • In-Network Compute Acceleration (INCA)

Lebenslauf

  • seit 2017

    Wissenschaftlicher Mitarbeiter am Fachgebiet ESA

  • 2015-2017

    M.Sc. Elektrotechnik und Informationstechnik, TU Darmstadt

  • 2015-2016

    Auslandsjahr, KTH Stockholm

  • 2012-2015

    B.Sc. Elektrotechnik und Informationstechnik, TU Darmstadt

Publications

  1. Heinz, C., and Koch, A. (2022). On-Chip and Distributed Dynamic Parallelism for Task-based Hardware Accelerators. Journal of Signal Processing Systems. doi: 10.1007/s11265-022-01759-2
    Preprint DOI
    Bibtex 
    @article{heinz2022jsps,
  author = {Heinz, Carsten and Koch, Andreas},
  title = {On-Chip and Distributed Dynamic Parallelism for Task-based Hardware Accelerators},
  journal = {Journal of Signal Processing Systems},
  year = {2022},
  month = apr,
  day = {29},
  issn = {1939-8115},
  doi = {10.1007/s11265-022-01759-2},
  preprint = {https://link.springer.com/content/pdf/10.1007/s11265-022-01759-2.pdf}
}
  2. Heinz, C., and Koch, A. (2021). Near-Data FPGA-Accelerated Processing of Collective and Inference Operations in Disaggregated Memory Systems. In 2021 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC).
    Preprint
    Bibtex 
    @inproceedings{heinz2021h2rc,
  title = {Near-Data FPGA-Accelerated Processing of Collective and Inference Operations in Disaggregated Memory Systems},
  author = {Heinz, Carsten and Koch, Andreas},
  booktitle = {2021 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)},
  year = {2021}
}
  3. Heinz, C., and Koch, A. (2021). Supporting On-Chip Dynamic Parallelism for Task-Based Hardware Accelerators. In S. Derrien, F. Hannig, P. C. Diniz, and D. Chillet (Eds.), Applied Reconfigurable Computing. Architectures, Tools, and Applications (pp. 81–92). Cham: Springer International Publishing.
    Preprint
    Bibtex 
    @inproceedings{heinz2021arc,
  author = {Heinz, Carsten and Koch, Andreas},
  editor = {Derrien, Steven and Hannig, Frank and Diniz, Pedro C. and Chillet, Daniel},
  title = {Supporting On-Chip Dynamic Parallelism for Task-Based Hardware Accelerators},
  booktitle = {Applied Reconfigurable Computing. Architectures, Tools, and Applications},
  year = {2021},
  publisher = {Springer International Publishing},
  address = {Cham},
  pages = {81--92},
  isbn = {978-3-030-79025-7}
}
  4. Heinz, C., Hofmann, J., Korinth, J., Sommer, L., Weber, L., and Koch, A. (2021). The TaPaSCo Open-Source Toolflow. Journal of Signal Processing Systems. doi: 10.1007/s11265-021-01640-8
    Preprint DOI
    Bibtex 
    @article{heinz2021jsps,
  author = {Heinz, Carsten and Hofmann, Jaco and Korinth, Jens and Sommer, Lukas and Weber, Lukas and Koch, Andreas},
  title = {The TaPaSCo Open-Source Toolflow},
  journal = {Journal of Signal Processing Systems},
  year = {2021},
  month = may,
  day = {02},
  issn = {1939-8115},
  doi = {10.1007/s11265-021-01640-8},
  preprint = {https://link.springer.com/content/pdf/10.1007/s11265-021-01640-8.pdf}
}
  5. Heinz, C., Hofmann, J. A., Sommer, L., and Koch, A. (2020). Improving Job Launch Rates in the TaPaSCo FPGA Middleware by Hardware/Software-Co-Design. In 2020 IEEE/ACM International Workshop on Runtime and Operating Systems for Supercomputers (ROSS) (pp. 22–30). doi: 10.1109/ROSS51935.2020.00008
    Preprint DOI
    Bibtex 
    @inproceedings{heinz2020ross,
  author = {{Heinz}, C. and {Hofmann}, J. A. and {Sommer}, L. and {Koch}, A.},
  booktitle = {2020 IEEE/ACM International Workshop on Runtime and Operating Systems for Supercomputers (ROSS)},
  title = {Improving Job Launch Rates in the TaPaSCo FPGA Middleware by Hardware/Software-Co-Design},
  year = {2020},
  volume = {},
  number = {},
  pages = {22-30},
  doi = {10.1109/ROSS51935.2020.00008}
}
  6. Heinz, C., Lavan, Y., Hofmann, J., and Koch, A. (2019). A Catalog and In-Hardware Evaluation of Open-Source Drop-In Compatible RISC-V Softcore Processors. In IEEE Proc. International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE.
    Preprint
    Bibtex 
    @inproceedings{heinz2019reconfig,
  title = {A Catalog and In-Hardware Evaluation of Open-Source Drop-In Compatible RISC-V Softcore Processors},
  author = {Heinz, Carsten and Lavan, Yannick and Hofmann, Jaco and Koch, Andreas},
  booktitle = {IEEE Proc. International Conference on ReConFigurable Computing and FPGAs (ReConFig)},
  year = {2019},
  organization = {IEEE}
}
  7. Korinth, J., Hofmann, J., Heinz, C., and Koch, A. (2019). The TaPaSCo Open-Source Toolflow for the Automated Composition of Task-Based Parallel Reconfigurable Computing Systems. In International Symposium on Applied Reconfigurable Computing (ARC).
    Preprint
    Bibtex 
    @inproceedings{korinth2019ttpscostactbprcs,
  title = {The TaPaSCo Open-Source Toolflow for the Automated Composition of Task-Based Parallel Reconfigurable Computing Systems},
  author = {Korinth, Jens and Hofmann, Jaco and Heinz, Carsten and Koch, Andreas},
  booktitle = {International Symposium on Applied Reconfigurable Computing (ARC)},
  year = {2019}
}
  8. Bühler, M., Heinz, C., and Kohaut, S. (2018). Dynamic Simulation Model for an Autonomous Sailboat. In S. M. Schillai and N. Townsend (Eds.), Robotic Sailing 2018 (pp. 31–39).
    Preprint Material
    Bibtex 
    @inproceedings{buhler2018dsmas,
  title = {{Dynamic Simulation Model for an Autonomous Sailboat}},
  author = {Bühler, Moritz and Heinz, Carsten and Kohaut, Simon},
  date = {2018},
  year = {2018},
  editor = {Schillai, Sophia M. and Townsend, Nicholas},
  booktitle = {Robotic Sailing 2018},
  booksubtitle = {Proceedings of the 11th International Robotic Sailing Conference},
  eventdate = {2018-08-31/2018-09-01},
  location = {Southampton, UK},
  pages = {31--39},
  preprint = {http://ceur-ws.org/Vol-2331/#paper3},
  material = {https://github.com/SailingTeamDarmstadt/stda-sailboat-simulator}
}