Staff photo for

Research Topics

  • Hardware Beschleuniger

Short CV

  • since 2020

    Graduate Research Associate in the Embedded Systems and Applications Group (ESA), TU Darmstadt

  • oct. 2019 - apr. 2020

    Internship, Xilinx

  • 2016-2018

    Master in Advanced Microelectronics, Politehnica University of Bucharest

  • june 2016 - oct. 2017

    Working Student, Infineon

  • 2012-2016

    Bachelor in Applied Electronics, Politehnica University of Bucharest

Publications

  1. Damian-Kosterhon, B. M., Meisel, F., and Koch, A. (2025). SCAL: An Open-Source Scalable Core Adaptation Layer for Interfacing RISC-V ISA Extensions. In 2025 IEEE 36th International Conference on Application-specific Systems, Architectures and Processors (ASAP) (pp. 73–80). doi: 10.1109/ASAP65064.2025.00020
    DOI
    Bibtex 
    @inproceedings{md2025asap,
  author = {Damian-Kosterhon, Brindusa Mihaela and Meisel, Florian and Koch, Andreas},
  booktitle = {2025 IEEE 36th International Conference on Application-specific Systems, Architectures and Processors (ASAP)},
  title = {SCAL: An Open-Source Scalable Core Adaptation Layer for Interfacing RISC-V ISA Extensions},
  year = {2025},
  volume = {},
  number = {},
  pages = {73-80},
  keywords = {Microarchitecture;Instruction sets;Semantics;Pipelines;Ecosystems;Systems architecture;Hazards;Resource management;SCAIE-V;ISAX;Portability;RISC-V},
  doi = {10.1109/ASAP65064.2025.00020}
}
  2. Damian-Kosterhon, B. M., Koch, A., Kosterhon, F., and Petrica, L. (2025). Improving mapping of convolutional neural networks on FPGAs through tailored macro sizes. In 2025 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) (pp. 1208–1215). doi: 10.1109/IPDPSW66978.2025.00193
    DOI
    Bibtex 
    @inproceedings{md2025raw,
  author = {Damian-Kosterhon, Brindusa Mihaela and Koch, Andreas and Kosterhon, Felix and Petrica, Lucian},
  booktitle = {2025 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)},
  title = {Improving mapping of convolutional neural networks on FPGAs through tailored macro sizes},
  year = {2025},
  volume = {},
  number = {},
  pages = {1208-1215},
  keywords = {Distributed processing;Linear regression;Rapid prototyping;Table lookup;Convolutional neural networks;Decision trees;High level languages;Field programmable gate arrays;Random forests;Binary sequences;FPGA;Floorplanning;PBlock;RapidWright;Neural Networks},
  doi = {10.1109/IPDPSW66978.2025.00193}
}
  3. Oppermann, J., Damian-Kosterhon, B. M., Meisel, F., Mürmann, T., Müller, P., Jentzsch, E., and Koch, A. (2024, October). Longnail: Hardware Synthesis of CoreDSL Custom Instructions for MCU- and Application-Class Cores. Poster presented at RISC-V Summit North America 2024.
    Poster
    Bibtex 
    @misc{meiselMuermann2024RVSummit,
  title = {Longnail: Hardware Synthesis of CoreDSL Custom Instructions for MCU- and Application-Class Cores},
  author = {Oppermann, Julian and Damian-Kosterhon, Brindusa Mihaela and Meisel, Florian and M\"{u}rmann, Tammo and M\"{u}ller, Philipp and Jentzsch, Eyck and Koch, Andreas},
  howpublished = {Poster presented at RISC-V Summit North America 2024},
  year = {2024},
  month = oct,
  location = {Santa Clara, CA, USA}
}
  4. Oppermann, J., Damian-Kosterhon, B. M., Meisel, F., Mürmann, T., Jentzsch, E., and Koch, A. (2024). Longnail: High-Level Synthesis of Portable Custom Instruction Set Extensions for RISC-V Processors from Descriptions in the Open-Source CoreDSL Language. In Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 3, ASPLOS ’24 (pp. 591–606). New York, NY, USA: Association for Computing Machinery. doi: 10.1145/3620666.3651375
    DOI URL Poster
    Bibtex 
    @inproceedings{oppermann2024asplos,
  author = {Oppermann, Julian and Damian-Kosterhon, Brindusa Mihaela and Meisel, Florian and M\"{u}rmann, Tammo and Jentzsch, Eyck and Koch, Andreas},
  title = {Longnail: High-Level Synthesis of Portable Custom Instruction Set Extensions for RISC-V Processors from Descriptions in the Open-Source CoreDSL Language},
  year = {2024},
  isbn = {9798400703867},
  publisher = {Association for Computing Machinery},
  address = {New York, NY, USA},
  url = {https://doi.org/10.1145/3620666.3651375},
  note = {Open Access},
  doi = {10.1145/3620666.3651375},
  booktitle = {Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 3},
  pages = {591–606},
  numpages = {16},
  location = {, La Jolla, CA, USA, },
  series = {ASPLOS '24}
}
  5. Damian, M., Oppermann, J., Spang, C., and Koch, A. (2022). SCAIE-V: An Open-Source SCAlable Interface for ISA Extensions for RISC-V Processors. In 2022 The 59th Design Automation Conference (DAC). doi: 10.1145/3489517.3530432
    HiPEAC Award Preprint DOI URL
    Bibtex 
    @inproceedings{damian2022dac,
  title = {SCAIE-V: An Open-Source SCAlable Interface for ISA Extensions for RISC-V Processors},
  author = {Damian, Mihaela and Oppermann, Julian and Spang, Christoph and Koch, Andreas},
  booktitle = {2022 The 59th Design Automation Conference (DAC)},
  year = {2022},
  url = {https://doi.org/10.1145/3489517.3530432},
  doi = {10.1145/3489517.3530432}
}
  6. Ecker, W., Adelt, P., Müller, W., Heckmann, R., Krstic, M., Herdt, V., Drechsler, R., et al. (2022). The Scale4Edge RISC-V Ecosystem. In 2022 Design, Automation & Test in Europe Conference (DATE). doi: 10.23919/DATE54114.2022.9774593
    Preprint DOI
    Bibtex 
    @inproceedings{s4e2022date,
  author = {Ecker, Wolfgang and Adelt, Peer and M{\"{u}}ller, Wolfgang and Heckmann, Reinhold and Krstic, Milos and Herdt, Vladimir and Drechsler, Rolf and Angst, Gerhard and Wimmer, Ralf and Mauderer, Andreas and Stahl, Rafael and Emrich, Karsten and Mueller{-}Gritschneder, Daniel and Becker, Bernd and Scholl, Philipp and Jentzsch, Eyck and Schlamelcher, Jan and Gr{\"{u}}ttner, Kim and Bernardo, Paul Palomero and Bringmann, Oliver and Damian, Mihaela and Oppermann, Julian and Koch, Andreas and Bormann, J{\"{o}}rg and Partzsch, Johannes and Mayr, Christian and Kunz, Wolfgang},
  title = {The Scale4Edge {RISC-V} Ecosystem},
  booktitle = {2022 Design, Automation {\&} Test in Europe Conference ({DATE})},
  year = {2022},
  doi = {10.23919/DATE54114.2022.9774593}
}