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Research Topics

  • High-Level Synthesis for FPGA-based accelerators
  • Domain- & application-specific FPGA accelerators and toolflows
  • Concurrent hardware architectures
  • Heterogeneous systems
  • Parallel programming

Short CV

  • 2011-2014

    Bachelor of Science in Computer Science, TU Darmstadt

  • 2014-2016

    Master of Science in Computer Science, TU Darmstadt

  • seit 2016

    Graduate Research Associate in the Embedded Systems and Applications Group (ESA), TU Darmstadt

Publications

  1. Hartmann, M., Weber, L., Wirth, J., Sommer, L., and Koch, A. (2021). Optimizing a Hardware Network Stack to Realize an In-Network ML Inference Application. In 2021 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC).
    Preprint Slides
    Bibtex
    @inproceedings{hartmann2021h2rc,
      title = {Optimizing a Hardware Network Stack to Realize an In-Network ML Inference Application},
      author = {Hartmann, Marco and Weber, Lukas and Wirth, Johannes and Sommer, Lukas and Koch, Andreas},
      booktitle = {2021 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)},
      year = {2021}
    }
    
  2. Sommer, L., Axenie, C., and Koch, A. (2021). SPNC: Fast Sum-Product Network Inference. In 2021 International Workshop on IoT, Edge, and Mobile for Embedded Machine Learning (ITEM).
    Preprint
    Bibtex
    @inproceedings{sommer2021item,
      author = {Sommer, Lukas and Axenie, Cristian and Koch, Andreas},
      booktitle = {2021 International Workshop on IoT, Edge, and Mobile for Embedded Machine Learning (ITEM)},
      title = {SPNC: Fast Sum-Product Network Inference},
      year = {2021},
      volume = {},
      number = {}
    }
    
  3. Weber, L., Sommer, L., Solis-Vasquez, L., Vinçon, T., Knödler, C., Bernhardt, A., Petrov, I., et al. (2021). A Framework for the Automatic Generation of FPGA-based Near-Data Processing Accelerators in Smart Storage Systems. In 2021 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) (pp. 136–143). doi: 10.1109/IPDPSW52791.2021.00028
    Preprint Slides Video
    Bibtex
    @inproceedings{weber2021raw,
      author = {Weber, Lukas and Sommer, Lukas and Solis-Vasquez, Leonardo and Vinçon, Tobias and Knödler, Christian and Bernhardt, Arthur and Petrov, Ilia and Koch, Andreas},
      booktitle = {2021 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)},
      title = {A Framework for the Automatic Generation of FPGA-based Near-Data Processing Accelerators in Smart Storage Systems},
      year = {2021},
      volume = {},
      number = {},
      pages = {136-143},
      doi = {10.1109/IPDPSW52791.2021.00028},
      video = {https://www.youtube.com/watch?v=8d6DkVJVwc0&list=PLewc2qlpcOueI2cuqtHqopIcmmLCU0Cvn&index=10&ab_channel=NECSTLab}
    }
    
  4. Sommer, L., Halkenhäuser, M., Axenie, C., and Koch, A. (2021). SPNC: Accelerating Sum-Product Network Inference on CPUs and GPUs. In 2021 IEEE 32th International Conference on Application-specific Systems, Architectures and Processors (ASAP). IEEE.
    Preprint
    Bibtex
    @inproceedings{sommer2021asap,
      title = {SPNC: Accelerating Sum-Product Network Inference on CPUs and GPUs},
      author = {Sommer, Lukas and Halkenhäuser, Michael and Axenie, Cristian and Koch, Andreas},
      booktitle = {2021 IEEE 32th International Conference on Application-specific Systems, Architectures and Processors (ASAP)},
      year = {2021},
      organization = {IEEE}
    }
    
  5. Kruppe, H., Sommer, L., Weber, L., Oppermann, J., Axenie, C., and Koch, A. (2021). Efficient Operator Sharing Modulo Scheduling for Sum-Product Network Inference on FPGAs. In Intl. Conf. on Embedded Computer Systems: Architectures, MOdeling and Simulation (SAMOS). Springer International Publishing.
    Preprint
    Bibtex
    @inproceedings{kruppe2021samos,
      title = {Efficient Operator Sharing Modulo Scheduling for Sum-Product Network Inference on FPGAs},
      author = {Kruppe, Hanna and Sommer, Lukas and Weber, Lukas and Oppermann, Julian and Axenie, Cristian and Koch, Andreas},
      booktitle = {Intl. Conf. on Embedded Computer Systems: Architectures, MOdeling and Simulation (SAMOS)},
      year = {2021},
      publisher = {Springer International Publishing}
    }
    
  6. Heinz, C., Hofmann, J., Korinth, J., Sommer, L., Weber, L., and Koch, A. (2021). The TaPaSCo Open-Source Toolflow. Journal of Signal Processing Systems. doi: 10.1007/s11265-021-01640-8
    Preprint
    Bibtex
    @article{heinz2021jsps,
      author = {Heinz, Carsten and Hofmann, Jaco and Korinth, Jens and Sommer, Lukas and Weber, Lukas and Koch, Andreas},
      title = {The TaPaSCo Open-Source Toolflow},
      journal = {Journal of Signal Processing Systems},
      year = {2021},
      month = may,
      day = {02},
      issn = {1939-8115},
      doi = {10.1007/s11265-021-01640-8},
      url = {https://doi.org/10.1007/s11265-021-01640-8},
      preprint = {https://link.springer.com/content/pdf/10.1007/s11265-021-01640-8.pdf}
    }
    
  7. Heinz, C., Hofmann, J. A., Sommer, L., and Koch, A. (2020). Improving Job Launch Rates in the TaPaSCo FPGA Middleware by Hardware/Software-Co-Design. In 2020 IEEE/ACM International Workshop on Runtime and Operating Systems for Supercomputers (ROSS) (pp. 22–30). doi: 10.1109/ROSS51935.2020.00008
    Preprint
    Bibtex
    @inproceedings{heinz2020ross,
      author = {{Heinz}, C. and {Hofmann}, J. A. and {Sommer}, L. and {Koch}, A.},
      booktitle = {2020 IEEE/ACM International Workshop on Runtime and Operating Systems for Supercomputers (ROSS)},
      title = {Improving Job Launch Rates in the TaPaSCo FPGA Middleware by Hardware/Software-Co-Design},
      year = {2020},
      volume = {},
      number = {},
      pages = {22-30},
      doi = {10.1109/ROSS51935.2020.00008}
    }
    
  8. Glaser, M., Macfarlane, C., May, B., Fleck, S., Sommer, L., Stavesand, J.-E., Weber, C., et al. (2020). Open standards enable continuous softwaredevelopment in the automotive industry. AutoSens Brussels.
    Preprint
    Bibtex
    @techreport{sommer2020autosens,
      author = {Glaser, Markus and Macfarlane, Charles and May, Benjamin and Fleck, Sven and Sommer, Lukas and Stavesand, Jann-Eve and Weber, Christian and Nguyen, Duong-Van and Ward, Enda and Rudkin, Ilya and Milz, Stefan and Oder, Rainer and Böhm, Frank and Schonlau, Benedikt and Hupfeld, Oliver and Koch, Andreas},
      title = {Open standards enable continuous softwaredevelopment in the automotive industry},
      institution = {AutoSens Brussels},
      year = {2020}
    }
    
  9. Huthmann, J., Podobas, A., Sommer, L., Koch, A., and Sano, K. (2020). Extending High-Level Synthesis with High-Performance Computing Performance Visualization. In 2020 IEEE International Conference on Cluster Computing (CLUSTER), CLUSTER ’20. Piscataway, NJ, USA: IEEE Press.
    Preprint
    Bibtex
    @inproceedings{huthmann2020cluster,
      author = {Huthmann, Jens and Podobas, Artur and Sommer, Lukas and Koch, Andreas and Sano, Kentaro},
      title = {Extending High-Level Synthesis with High-Performance Computing Performance Visualization},
      booktitle = {2020 IEEE International Conference on Cluster Computing (CLUSTER)},
      series = {CLUSTER '20},
      year = {2020},
      location = {Kobe, Japan},
      publisher = {IEEE Press},
      address = {Piscataway, NJ, USA}
    }
    
  10. Sommer, L., and Koch, A. (2020). OpenMP Device Offloading for Embedded Heterogeneous Platforms - Work-in-Progress. In Proceedings of the International Conference on Embedded Software, EMSOFT ’20. Piscataway, NJ, USA: IEEE Press.
    Preprint
    Bibtex
    @inproceedings{sommer2020emsoft,
      author = {Sommer, Lukas and Koch, Andreas},
      title = {OpenMP Device Offloading for Embedded Heterogeneous Platforms - Work-in-Progress},
      booktitle = {Proceedings of the International Conference on Embedded Software},
      series = {EMSOFT '20},
      year = {2020},
      location = {New York, NY, USA},
      publisher = {IEEE Press},
      address = {Piscataway, NJ, USA}
    }
    
  11. Huthmann, J., Sommer, L., Podobas, A., Koch, A., and Sano, K. (2020). OpenMP Device Offloading to FPGAs using the Nymble Infrastructure. In K. Miltfield, B. R. de Supinski, L. Koesterke, and J. Klinkenberg (Eds.), OpenMP: Portable Multi-level Parallelism on Modern Systems. Cham: Springer International Publishing.
    Preprint
    Bibtex
    @inproceedings{huthmann2020iwomp,
      author = {Huthmann, Jens and Sommer, Lukas and Podobas, Artur and Koch, Andreas and Sano, Kentaro},
      title = {OpenMP Device Offloading to FPGAs using the Nymble Infrastructure},
      editor = {Miltfield, Kent and de Supinski, Bronis R. and Koesterke, Lars and Klinkenberg, Jannis},
      booktitle = {OpenMP: Portable Multi-level Parallelism on Modern Systems},
      year = {2020},
      publisher = {Springer International Publishing},
      address = {Cham}
    }
    
  12. Sommer, L., Stock, F., Solis-Vasquez, L., and Koch, A. (2020). DAPHNE - An Automotive Benchmark Suite for Parallel Programming Models on Embedded Heterogeneous Platforms. In D. Ziegenbein, S. Saidi, X. S. Hu, and S. Steinhorst (Eds.), Future Automotive HW/SW Platform Design (Dagstuhl Seminar 19502), Dagstuhl Reports (Vol. 9, pp. 28–66). Dagstuhl, Germany: Schloss Dagstuhl–Leibniz-Zentrum fuer Informatik. doi: 10.4230/DagRep.9.12.28
    Preprint
    Bibtex
    @inproceedings{sommer2020dagstuhl,
      author = {Sommer, Lukas and Stock, Florian and Solis-Vasquez, Leonardo and Koch, Andreas},
      title = {DAPHNE - An Automotive Benchmark Suite for Parallel Programming Models on Embedded Heterogeneous Platforms},
      booktitle = {{{Future Automotive HW/SW Platform Design (Dagstuhl Seminar 19502)}}},
      year = {2020},
      editor = {Ziegenbein, Dirk and Saidi, Selma and Hu, Xiaobo Sharon and Steinhorst, Sebastian},
      volume = {9},
      series = {Dagstuhl Reports},
      pages = {28--66},
      publisher = {{Schloss Dagstuhl--Leibniz-Zentrum fuer Informatik}},
      address = {Dagstuhl, Germany},
      url = {https://drops.dagstuhl.de/opus/volltexte/2020/12010},
      urn = {urn:nbn:de:0030-drops-120101},
      doi = {10.4230/DagRep.9.12.28},
      annote = {Keywords: automotive, hw/sw platforms, real-time systems, systems design automation},
      preprint = {http://dx.doi.org/10.4230/DagRep.9.12.28}
    }
    
  13. Sommer, L., Weber, L., Kumm, M., and Koch, A. (2020). Comparison of Arithmetic Number Formats for Inference in Sum-Product Networks on FPGAs. In 2020 IEEE 28th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) (pp. 1–10).
    Best Paper Award, HiPEAC Award Preprint Slides Video
    Bibtex
    @inproceedings{sommer2020fccm,
      author = {Sommer, Lukas and Weber, Lukas and Kumm, Martin and Koch, Andreas},
      booktitle = {2020 IEEE 28th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)},
      title = {Comparison of Arithmetic Number Formats for Inference in Sum-Product Networks on FPGAs},
      year = {2020},
      pages = {1-10},
      video = {http://www.fccm.org/past/2020/forums/topic/comparison-of-arithmetic-number-formats-for-inference-in-sum-product-networks-on/}
    }
    
  14. Sommer, L., Stock, F., Solis-Vasquez, L., and Koch, A. (2020). Using Parallel Programming Models for Automotive Workloads on Heterogeneous Systems - a Case Study. In 28th EUROMICRO International Conference on Parallel, Distributed and Network-Based Processing (PDP’20).
    Preprint
    Bibtex
    @inproceedings{sommer2020pdp,
      author = {Sommer, Lukas and Stock, Florian and Solis-Vasquez, Leonardo and Koch, Andreas},
      booktitle = {28th EUROMICRO International Conference on Parallel, Distributed and Network-Based Processing (PDP'20)},
      title = {Using Parallel Programming Models for Automotive Workloads on Heterogeneous Systems - a Case Study},
      year = {2020},
      keywords = {embedded, automotive, parallel programming, heterogeneous, OpenMP, OpenCL, CUDA}
    }
    
  15. Weber, L., Sommer, L., Oppermann, J., Molina, A., Kersting, K., and Koch, A. (2019). Resource-Efficient Logarithmic Number Scale Arithmetic for SPN Inference on FPGAs. In International Conference on Field-Programmable Technology (FPT).
    Preprint Slides Poster
    Bibtex
    @inproceedings{weber2019relnsafsiof,
      title = {Resource-Efficient Logarithmic Number Scale Arithmetic for SPN Inference on FPGAs},
      author = {Weber, Lukas and Sommer, Lukas and Oppermann, Julian and Molina, Alejandro and Kersting, Kristian and Koch, Andreas},
      booktitle = {International Conference on Field-Programmable Technology (FPT)},
      year = {2019}
    }
    
  16. Oppermann, J., Sommer, L., Weber, L., Reuter-Oppermann, M., Koch, A., and Sinnen, O. (2019). SkyCastle: A Resource-Aware Multi-Loop Scheduler for High-Level Synthesis. In International Conference on Field-Programmable Technology (FPT).
    Preprint Slides
    Bibtex
    @inproceedings{oppermann2019scamlsfhls,
      title = {SkyCastle: A Resource-Aware Multi-Loop Scheduler for High-Level Synthesis},
      author = {Oppermann, Julian and Sommer, Lukas and Weber, Lukas and Reuter-Oppermann, Melanie and Koch, Andreas and Sinnen, Oliver},
      booktitle = {International Conference on Field-Programmable Technology (FPT)},
      year = {2019}
    }
    
  17. Ober, M., Hofmann, J., Sommer, L., Weber, L., and Koch, A. (2019). High-Throughput Multi-Threaded Sum-Product Network Inference in the Reconfigurable Cloud. In Fifth International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC).
    Preprint
    Bibtex
    @inproceedings{ober2019h2rc,
      title = {High-Throughput Multi-Threaded Sum-Product Network Inference in the Reconfigurable Cloud},
      author = {Ober, Micha and Hofmann, Jaco and Sommer, Lukas and Weber, Lukas and Koch, Andreas},
      booktitle = {Fifth International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)},
      year = {2019}
    }
    
  18. Sommer, L., Stock, F., Solis-Vasquez, L., and Koch, A. (2019). Work-in-Progress: DAPHNE - Automotive Benchmark Suite for Parallel Programming Models on Embedded Heterogeneous Platforms. In Proceedings of the International Conference on Embedded Software (accepted for publication 07/2019), EMSOFT ’19. Piscataway, NJ, USA: IEEE Press.
    Preprint
    Bibtex
    @inproceedings{emsoft2019,
      author = {Sommer, Lukas and Stock, Florian and Solis-Vasquez, Leonardo and Koch, Andreas},
      title = {Work-in-Progress: DAPHNE - Automotive Benchmark Suite for Parallel Programming Models on Embedded Heterogeneous Platforms},
      booktitle = {Proceedings of the International Conference on Embedded Software (accepted for publication 07/2019)},
      series = {EMSOFT '19},
      year = {2019},
      location = {New York, NY, USA},
      publisher = {IEEE Press},
      address = {Piscataway, NJ, USA}
    }
    
  19. Sommer, L., Stock, F., Solis-Vasquez, L., and Koch, A. (2019). EPHoS: Evaluation of Programming - Models for Heterogeneous Systems. FAT-Schriftenreihe 317. Forschungsvereinigung Automobiltechik.
    Preprint
    Bibtex
    @article{fat317,
      title = {EPHoS: Evaluation of Programming - Models for Heterogeneous Systems},
      author = {Sommer, Lukas and Stock, Florian and Solis-Vasquez, Leonardo and Koch, Andreas},
      booktitle = {FAT-Schriftenreihe 317},
      year = {2019},
      publisher = {Forschungsvereinigung Automobiltechik},
      preprint = {https://www.vda.de/de/services/Publikationen/fat-schriftenreihe-317.html}
    }
    
  20. Oppermann, J., Reuter-Oppermann, M., Sommer, L., Koch, A., and Sinnen, O. (2019). Exact and Practical Modulo Scheduling for High-Level Synthesis. TRETS, 12(2), 8:1–8:26. doi: 10.1145/3317670
    Preprint
    Bibtex
    @article{oppermann2019epmshs,
      author = {Oppermann, Julian and Reuter{-}Oppermann, Melanie and Sommer, Lukas and Koch, Andreas and Sinnen, Oliver},
      title = {Exact and Practical Modulo Scheduling for High-Level Synthesis},
      journal = {{TRETS}},
      volume = {12},
      number = {2},
      pages = {8:1--8:26},
      year = {2019},
      doi = {10.1145/3317670}
    }
    
  21. Halkenhäuser, M., and Sommer, L. (2019). An alternative OpenMP Backend for Polly. In 2019 European LLVM Developers Meeting.
    Preprint
    Bibtex
    @inproceedings{halkenhaeuser2019aompbp,
      title = {An alternative OpenMP Backend for Polly},
      author = {Halkenhäuser, Michael and Sommer, Lukas},
      booktitle = {2019 European LLVM Developers Meeting},
      year = {2019}
    }
    
  22. Kruppe, R., Oppermann, J., Sommer, L., and Koch, A. (2019). Extending LLVM for Lightweight SPMD Vectorization: Using SIMD and Vector Instructions Easily from Any Language . In 2019 International Symposium on Code Generation and Optimization.
    Preprint
    Bibtex
    @inproceedings{kruppe2019ellvmlspmdvusimdvieal,
      title = {Extending LLVM for Lightweight SPMD Vectorization: Using SIMD and Vector Instructions Easily from Any Language },
      author = {Kruppe, Robin and Oppermann, Julian and Sommer, Lukas and Koch, Andreas},
      booktitle = {2019 International Symposium on Code Generation and Optimization},
      year = {2019}
    }
    
  23. Sommer, L., Oppermann, J., Molina, A., Binnig, C., Kersting, K., and Koch, A. (2018). Automatic Mapping of the Sum-Product Network Inference Problem to FPGA-based Accelerators. In IEEE International Conference on Computer Design (ICCD). IEEE.
    Preprint
    Bibtex
    @inproceedings{sommer2018amspnipfpgaa,
      title = {Automatic Mapping of the Sum-Product Network Inference Problem to FPGA-based Accelerators},
      author = {Sommer, Lukas and Oppermann, Julian and Molina, Alejandro and Binnig, Carsten and Kersting, Kristian and Koch, Andreas},
      booktitle = {IEEE International Conference on Computer Design (ICCD)},
      year = {2018},
      organization = {IEEE}
    }
    
  24. Oppermann, J., Reuter-Oppermann, M., Sommer, L., Sinnen, O., and Koch, A. (2018). Dependence Graph Preprocessing for Faster Exact Modulo Scheduling in High-level Synthesis. In Intl. Conf. on Field Programmable Logic and Applications (FPL).
    Preprint Slides
    Bibtex
    @inproceedings{oppermann2018dgpfemshs,
      title = {Dependence Graph Preprocessing for Faster Exact Modulo Scheduling in High-level Synthesis},
      author = {Oppermann, Julian and Reuter-Oppermann, Melanie and Sommer, Lukas and Sinnen, Oliver and Koch, Andreas},
      booktitle = {Intl. Conf. on Field Programmable Logic and Applications (FPL)},
      year = {2018}
    }
    
  25. Sommer, L., Oppermann, J., Molina, A., Binnig, C., Kersting, K., and Koch, A. (2018). Automatic Synthesis of FPGA-based Accelerators for the Sum-Product Network Inference Problem. In ICML 2018 Workshop on Tractable Probabilistic Models (TPM). ICML.
    Preprint
    Bibtex
    @inproceedings{sommer2018asfpgaaspnip,
      title = {Automatic Synthesis of FPGA-based Accelerators for the Sum-Product Network Inference Problem},
      author = {Sommer, Lukas and Oppermann, Julian and Molina, Alejandro and Binnig, Carsten and Kersting, Kristian and Koch, Andreas},
      booktitle = {ICML 2018 Workshop on Tractable Probabilistic Models (TPM)},
      year = {2018},
      organization = {ICML}
    }
    
  26. Sommer, L., Oppermann, J., Korinth, J., and Koch, A. (2018). Offloading OpenMP Target Regions to FPGA Accelerators Using LLVM. In 2018 European LLVM Developers Meeting.
    Preprint
    Bibtex
    @inproceedings{sommer2018oomptrfpgaaullvm,
      title = {Offloading OpenMP Target Regions to FPGA Accelerators Using LLVM},
      author = {Sommer, Lukas and Oppermann, Julian and Korinth, Jens and Koch, Andreas},
      booktitle = {2018 European LLVM Developers Meeting},
      year = {2018}
    }
    
  27. Sommer, L., Oppermann, J., Hofmann, J., and Koch, A. (2017). Synthesis of Interleaved Multithreaded Accelerators from OpenMP Loops. In 2017 International Conference on Reconfigurable Computing and FPGAs (ReConFig’17). IEEE.
    Preprint
    Bibtex
    @inproceedings{sommer2017simaompl,
      title = {Synthesis of Interleaved Multithreaded Accelerators from OpenMP Loops},
      author = {Sommer, Lukas and Oppermann, Julian and Hofmann, Jaco and Koch, Andreas},
      booktitle = {2017 International Conference on Reconfigurable Computing and FPGAs (ReConFig'17)},
      year = {2017},
      organization = {IEEE}
    }
    
  28. Sommer, L., Korinth, J., and Koch, A. (2017). OpenMP Device Offloading to FPGA Accelerators. In International Conference on Application-specific Systems, Architectures and Processors (ASAP).
    Preprint Poster
    Bibtex
    @inproceedings{sommer2017ompdofpgaa,
      title = {OpenMP Device Offloading to FPGA Accelerators},
      author = {Sommer, Lukas and Korinth, Jens and Koch, Andreas},
      booktitle = {International Conference on Application-specific Systems, Architectures and Processors (ASAP)},
      year = {2017}
    }
    
  29. Oppermann, J., Sommer, L., and Koch, A. (2017). SpExSim: assessing kernel suitability for C-based high-level hardware synthesis. In Journal of Supercomputing.
    Preprint
    Bibtex
    @inproceedings{oppermann2017sesc,
      title = {SpExSim: assessing kernel suitability for C-based high-level hardware synthesis},
      author = {Oppermann, Julian and Sommer, Lukas and Koch, Andreas},
      booktitle = {Journal of Supercomputing},
      year = {2017},
      preprint = {http://link.springer.com/article/10.1007/s11227-017-2101-z}
    }
    
  30. Sommer, L., Oppermann, J., and Koch, A. (2016). C-based Synthesis of Area-Efficient Accelerators for OpenMP Worksharing Loops. In Second International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC).
    Preprint
    Bibtex
    @inproceedings{sommer2016csaeaompwl,
      title = {C-based Synthesis of Area-Efficient Accelerators for OpenMP Worksharing Loops},
      author = {Sommer, Lukas and Oppermann, Julian and Koch, Andreas},
      booktitle = {Second International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)},
      year = {2016}
    }