Als eine Gruppe der Technischen Informatik arbeiten wir an der Schnittstelle von Hardware und Software. Der Schwerpunkt unser aktuellen Forschung liegt dabei auf der effizienten Bereitstellung von Rechenleistung. Effizient heisst hier, dass die in diversen Anwendungsgebieten erforderliche Rechenleistung nicht oder nur mit hohem Energieverbrauch von Standardprozessoren bereitgestellt werden kann.

Als Alternative schlagen wir adaptive Computer vor, die einen kleineren, energieeffizienten Standardprozessor mit einer hoch optimierten rekonfigurierbaren Recheneinheit kombinieren. Letztere kann in ihrer Struktur optimal an die Anforderungen der aktuellen Anwendung angepasst werden und so die Spitzenlast der Rechenleistung bei niedrigerem Energieverbrauch bereitstellen.

Um dieses Ziel zu erreichen, realisieren wir Hardware-Erprobungsplattformen für solche Rechnerarchitekturen (einschließlich der erforderlichen Betriebssystemanpassungen) und erproben diese dann anhand von praktischen Anwendungen. Nach den sehr vielversprechenden Ergebnissen dieser Untersuchungen haben wir unser Augenmerk nun darauf gerichtet, die Programmierbarkeit adaptiver Computer so zu verbessern, dass sie auch von Entwicklern ohne Kenntnisse des Hardware-Entwurfs genutzt werden können. Dazu entsteht ein kompletter Compiler-Fluss, der eine Hochsprache automatisch auf die beiden Recheneinheiten aufteilt. Der an die rekonfigurierbare Recheneinheit zugewiesene Teil wird dann mit Methoden der Hardware-Synthese und des Chip-Entwurfs (Mapping, Platzierung, Verdrahtung) automatisch in eine dort ausführbare Struktur transformiert.

Da wir für dieses Unterfangen natürlich auf die Mitarbeit durch interessierte Studierende mit entsprechenden Vorkenntnissen angewiesen sind, werden für diese Themen auch einführende Lehrveranstaltungen entwickelt.

News

  • Best Paper Award at DASIP 2023

    Our work TaPaFuzz - An FPGA-Accelerated Framework for RISC-V IoT Graybox Fuzzing has won the Best Paper Award at DASIP 2023. We are extremely happy. Thanks to the committee for selecting our work!

    By Florian Meisel, 20.01.2023


  • Invited Talk at Global RISC-V Summit 2022

    After a highly competitive selection process (13% acceptance rate), ESA researchers Mihaela Damian, Julian Oppermann, Christoph Spang and Andreas Koch were chosen for presenting their SCAIE-V scalable and portable interface for adding custom instructions to RISC-V processors at the 2022 Global RISC-V Summit.

    The RISC-V Summit is the key global event for presenting advances around the open RISC-V processor instruction set architecture (ISA), which is shaping up to be a viable alternative to the existing proprietary solutions in a number of application domains.

    The SCAIE-V interface developed by the ESA Group provides a standardized way to extend the base RISC-V instruction set with specialized instructions, for example, for application domains such as machine learning, IT security, or digital signal processing. This specialization can be used to improve the performance and/or energy efficiency of the customized processors. Using SCAIE-V, these specialized instructions can easily be attached to different base processor cores, with the interface automatically scaling to the needs of the actual custom instructions used.

    A video of the presentation is available, which is based on an earlier research paper presented at the DAC 2022 conference.

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    By Prof. Dr-Ing. Andreas Koch, 4.01.2023


  • Best Paper Award at ICACGA 2022 in Denver

    Our work GAAlign: Robust Sampling-based Point Cloud Registration using Geometric Algebra has won a Best Paper Award (GA Applied to Computational Performance) at ICACGA 2022. We are extremely happy. Thanks to the committee for selecting our work!

    By Dr.-Ing. Florian Stock, 5.10.2022


  • ESA wins Best Paper Award at FPL 2022

    We are glad that our paper “DeLiBA: An Open-Source Hardware/Software Framework for the Development of Linux Block I/O Accelerators” wins the best paper award at FPL 2022 conference. The award was presented during the banquet on Tuesday 30th August by the Chair of the Best Paper Award Committee at Belfast, UK. Congratulations to the other nominees for their excellent research work.

    By Babar Khan, 8.09.2022


  • Two ESA papers get accepted at FPL 2022

    We are very happy to announce that two submitted papers of our group have been accepted for presentation at FPL 2022

    The first paper entitled DeLiBA: An Open-Source Hardware/Software Framework for the Development of Linux Block I/O Accelerators – by Babar Khan, Carsten Heinz, and Andreas Koch – is a result of the SODDAS project. DeLiBA aims to address Linux block I/O acceleration by allowing development of software components of the I/O stack in the user space instead of the kernel space, and leverages a proven FPGA SoC framework to quickly compose and deploy the actual FPGA-based I/O accelerators. The framework uses a software-defined distributed storage protocol, namely Ceph, for the proof-of-concept implementation.

    The second paper entitled Direct Device-to-Device Physical Page Migrations in Multi-FPGA Shared Virtual Memory Systems – by Torben Kalkhof and Andreas Koch – extends the TaPaSCo SVM feature by introducing Shared Virtual Memory (SVM) with physical page migrations to multi-FPGA architectures. Three different data transfer mechanisms for the additional direct device-to-device page migrations are examined in this work: a two-step copy approach via PCIe and a bounce buffer in host memory, direct PCIe endpoint-to-endpoint transfers, and data transfers over a 100G Ethernet connection.

    Congratulations and keep up the good work everyone!

    By Torben Kalkhof, 20.07.2022


  • ESA paper gets accepted at DAC 2022

    We are very happy to announce that our submitted paper has been accepted for presentation at DAC 2022.

    This paper entitled SCAIE-V: An Open-Source SCAlable Interface for ISA Extensions for RISC-V Processors –- by Mihaela Damian, Julian Oppermann, Christoph Spang and Andreas Koch -– is a result of the Scale4Edge project. The paper presents a new scalable interface named SCAIE-V, which integrates custom instructions into RISC-V cores. Currently, the project supports 4 cores (Piccolo, PicoRV32, VexRiscv and ORCA) for which the custom instructions can be integrated automatically. The interface can interact with the core’s register file, program counter as well as memory bus. The corresponding logic is added only if it is required by the custom instruction. Moreover, SCAIE-V supports decoupled instructions, which run in parallel to the main pipeline. All these features facilitate a faster integration of ISA extensions while reaching for a low hardware penalty.

    By Brindusa Mihaela Damian, 24.03.2022


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