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(Short-)CV

  • since 2022

    Research Associate at the Embedded Systems and Applications Group (ESA)

  • 2020-2022

    M.Sc. Computer Science, TU Darmstadt

  • 2017-2020

    B.Sc. Computer Science, TU Darmstadt

Publications

  1. Oppermann, J., Damian-Kosterhon, B. M., Meisel, F., Mürmann, T., Jentzsch, E., and Koch, A. (2024). Longnail: High-Level Synthesis of Portable Custom Instruction Set Extensions for RISC-V Processors from Descriptions in the Open-Source CoreDSL Language. In Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 3, ASPLOS ’24 (pp. 591–606). New York, NY, USA: Association for Computing Machinery. doi: 10.1145/3620666.3651375
    DOI URL
    Bibtex
    @inproceedings{oppermann2024asplos,
      author = {Oppermann, Julian and Damian-Kosterhon, Brindusa Mihaela and Meisel, Florian and M\"{u}rmann, Tammo and Jentzsch, Eyck and Koch, Andreas},
      title = {Longnail: High-Level Synthesis of Portable Custom Instruction Set Extensions for RISC-V Processors from Descriptions in the Open-Source CoreDSL Language},
      year = {2024},
      isbn = {9798400703867},
      publisher = {Association for Computing Machinery},
      address = {New York, NY, USA},
      url = {https://doi.org/10.1145/3620666.3651375},
      doi = {10.1145/3620666.3651375},
      booktitle = {Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 3},
      pages = {591–606},
      numpages = {16},
      location = {, La Jolla, CA, USA, },
      series = {ASPLOS '24}
    }
    
  2. Meisel, F., Volz, D., Spang, C., Tran, D., and Koch, A. (2023). TaPaFuzz - An FPGA-Accelerated Framework for RISC-V IoT Graybox Fuzzing. In Workshop on Design and Architectures for Signal and Image Processing, DASIP ’23. Springer International Publishing.
    Best Paper Award Preprint
    Bibtex
    @inproceedings{fm2023dasip,
      author = {Meisel, Florian and Volz, David and Spang, Christoph and Tran, Dat and Koch, Andreas},
      title = {TaPaFuzz - An FPGA-Accelerated Framework for RISC-V IoT Graybox Fuzzing},
      booktitle = {Workshop on Design and Architectures for Signal and Image Processing},
      series = {DASIP '23},
      year = {2023},
      publisher = {Springer International Publishing}
    }
    
  3. Spang, C., Lavan, Y., Hartmann, M., Meisel, F., and Koch, A. (2022). DExIE - An IoT-Class Hardware Monitor for Real-Time Fine-Grained Control-Flow Integrity. In Journal of Signal Processing Systems (Vol. 94, pp. 739–752). doi: 10.1007/s11265-021-01732-5
    Preprint DOI URL
    Bibtex
    @inproceedings{spang2022jsps,
      author = {Spang, Christoph and Lavan, Yannick and Hartmann, Marco and Meisel, Florian and Koch, Andreas},
      title = {DExIE - An IoT-Class Hardware Monitor for Real-Time Fine-Grained Control-Flow Integrity},
      journal = {Journal of Signal Processing Systems},
      year = {2022},
      month = jul,
      day = {01},
      volume = {94},
      number = {7},
      pages = {739-752},
      issn = {1939-8115},
      doi = {10.1007/s11265-021-01732-5},
      url = {https://doi.org/10.1007/s11265-021-01732-5}
    }
    
  4. Spang, C., Meisel, F., and Koch, A. (2021). RT-LIFE: Portable RISC-V Interface for Real-Time Lightweight Security Enforcement. In Intl. Conf. on Embedded Computer Systems: Architectures, MOdeling and Simulation (SAMOS). Springer International Publishing.
    Preprint Slides
    Bibtex
    @inproceedings{spang2021samos,
      title = {RT-LIFE: Portable RISC-V Interface for Real-Time Lightweight Security Enforcement},
      author = {Spang, Christoph and Meisel, Florian and Koch, Andreas},
      booktitle = {Intl. Conf. on Embedded Computer Systems: Architectures, MOdeling and Simulation (SAMOS)},
      year = {2021},
      publisher = {Springer International Publishing}
    }
    
  5. Spang, C., Lavan, Y., Hartmann, M., Meisel, F., and Koch, A. (2021). DExIE - An IoT-Class Hardware Monitor for Real-Time Fine-Grained Control-Flow Integrity. In Workshop on Design and Architectures for Signal and Image Processing (14th Edition), DASIP ’21 (pp. 26–34). New York, NY, USA: Association for Computing Machinery. doi: 10.1145/3441110.3441146
    Best Paper Award Preprint DOI URL Slides
    Bibtex
    @inproceedings{spang2021dasip,
      author = {Spang, Christoph and Lavan, Yannick and Hartmann, Marco and Meisel, Florian and Koch, Andreas},
      title = {DExIE - An IoT-Class Hardware Monitor for Real-Time Fine-Grained Control-Flow Integrity},
      year = {2021},
      isbn = {9781450389013},
      publisher = {Association for Computing Machinery},
      address = {New York, NY, USA},
      url = {https://doi.org/10.1145/3441110.3441146},
      doi = {10.1145/3441110.3441146},
      booktitle = {Workshop on Design and Architectures for Signal and Image Processing (14th Edition)},
      pages = {26–34},
      numpages = {9},
      keywords = {Fine-Grained Control Flow Integrity, IoT, Real Time, RISC-V, Hardware Security, Low Overhead},
      location = {Budapest, Hungary},
      series = {DASIP '21}
    }