![]() | Prof. Dr.-Ing. Andreas Koch | ||
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Technische Universität Darmstadt | |||
FB20 (Dept. of Computer Science) | |||
Embedded Systems and Applications Group (ESA) | |||
Hochschulstr. 10 | |||
D-64289 Darmstadt | |||
Germany | |||
Phone: +49 6151 / 16-22420 | |||
Fax: +49 6151 / 16-22422 | |||
E-Mail: | ![]() | ||
S2/02 (Piloty-Building), Room E101 |
Research Areas
Andreas Koch is performing research in the area of specialized computing systems, sometimes called application-specific or domain-specific architectures. These specialized computers, which can range from ultra-low power embedded systems up to data-center high-performance computers, often improve upon general purpose systems (e.g., PCs or servers) with better performance, energy efficiency, or security. Dr. Koch does not just work on the internal architecture for such systems, but also on the programming tools required for their actual use. This includes high-level methods such as domain-specific languages and compilers, as well as low-level tools from the areas of Electronic Design Automation (e.g., place&route, scheduling etc.).CV
- 1992
- Diploma in Informatics (TU Braunschweig, Germany)
- 1997
- Doctorate in Engineering (Dr.-Ing.) (TU Braunschweig, EIS)
- 1997-1999
- Post-Doc Researcher (UC Berkeley, CS Department, BRASS Group)
- 1999
- Senior Post-Doc Researcher (TU Braunschweig, EIS)
- 2005
- Associate Professor at TU Darmstadt
- 2012
- Full Professor at TU Darmstadt
Publications
2019
Lukas Sommer, Florian Stock, Leonardo Solis-Vasquez, Andreas KochEPHoS: Evaluation of Programming Models for Heterogeneous Systems
FAT Schriftenreihe 317, Forschungsvereinigung Automobiltechnik, 2019

The TaPaSCo Open-Source Toolflow for the Automated Composition of Task-Based Parallel Reconfigurable Computing Systems
International Symposium on Applied Reconfigurable Computing (ARC), Darmstadt (Germany), 2019
Julian Oppermann, Melanie Reuter-Oppermann, Lukas Sommer, Andreas Koch, Oliver Sinnen
Exact and Practical Modulo Scheduling for High-level Synthesis
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Accepted, currently in production Michael Halkenhäuser, Lukas Sommer
An alternative OpenMP Backend for Polly
2019 European LLVM Developers Meeting, Brussels, BE, 04-2019

Adventures with RISC-V Vectors and LLVM
2019 European LLVM Developers Meeting, Brussels, BE, 04-2019
Robin Kruppe, Julian Oppermann, Lukas Sommer, Andreas Koch
Extending LLVM for Lightweight SPMD Vectorization: Using SIMD and Vector Instructions Easily from Any Language
2019 International Symposium on Code Generation and Optimization, Washington, D.C., US, 02-2019

2018
Lukas Sommer, Julian Oppermann, Alejandro Molina, Carsten Binnig, Kristian Kersting, Andreas KochAutomatic Mapping of the Sum-Product Network Inference Problem to FPGA-based Accelerators
IEEE International Conference on Computer Design (ICCD), Orlando, FL, USA, 10-2018

A Case Study in Using OpenCL on FPGAs: Creating an Open-Source Accelerator of the AutoDock Molecular Docking Software
Fifth International Workshop on FPGAs for Software Programmers (FSP), Dublin, Ireland, 08-2018


Work in Progress: GeMS: A Generator for Modulo Scheduling Problems
Intl. Conf. on Compilers, Architectures and Synthesis For Embedded Systems (CASES), ESWEEK, Torino, IT, 09-2018

Consensus for Non-volatile Main Memory
2018 IEEE 26th International Conference on Network Protocols (ICNP)

Dependence Graph Preprocessing for Faster Exact Modulo Scheduling in High-level Synthesis
Intl. Conf. on Field Programmable Logic and Applications (FPL), Dublin, Ireland, 08-2018

ILP-based Modulo Scheduling and Binding for Register Minimization
Intl. Conf. on Field Programmable Logic and Applications (FPL), Dublin, Ireland, 08-2018

HatScheT: A Contribution to Agile HLS
FPGAs for Software Programmers (FSP), Dublin, Ireland, 08-2018

Automatic Synthesis of FPGA-based Accelerators for the Sum-Product Network Inference Problem
ICML 2018 Workshop on Tractable Probabilistic Models (TPM), Stockholm, Sweden, 07-2018

Supporting the RISC-V Vector Extensions in LLVM
2018 European LLVM Developers Meeting, Bristol, UK, 04-2018



Offloading OpenMP Target Regions to FPGA Accelerators Using LLVM
2018 European LLVM Developers Meeting, Bristol, UK, 04-2018

NoFTL-KV: Tackling Write-Amplification on KV-Stores with Native Storage Management
Proc. of the 21st International Conference on Extending Database Technology (EDBT), 03-2018

A Real-Time Reconfigurable Multichip Architecture for Large-Scale Biophysically Accurate Neuron Simulation
IEEE Transactions on Biomedical Circuits and Systems, 01-2018

Improved High-Level Synthesis for Complex CellML Models
Proc. 14th International Symposium on Applied Reconfigurable Computing (ARC), Santorini (Greece), 05-2018

2017
Andreas Engel, Andreas KochEnergy-Efficient Reconfiguration of Flash-based FPGAs in Heterogeneous Wireless Sensor Nodes
IEEE Proc. International Conference on ReConFigurable Computing and FPGAs (ReConFig), Cancun, Mexico, 12-2017

Synthesis of Interleaved Multithreaded Accelerators from OpenMP Loops
2017 International Conference on Reconfigurable Computing and FPGAs (ReConFig'17), Cancun (Mexico), 12-2017

OpenMP Device Offloading to FPGA Accelerators
International Conference on Application-specific Systems, Architectures and Processors (ASAP), Seattle (USA), 07-2017


SpExSim: assessing kernel suitability for C-based high-level hardware synthesis
Journal of Supercomputing, 07-2017

A Performance and Energy Evaluation of OpenCL-accelerated Molecular Docking
Fifth International Workshop on OpenCL (IWOCL), Toronto (Canada), 05-2017


2016
Björn Liebig, Andreas KochHigh-Level Synthesis of Resource-Shared Microarchitectures from Irregular Complex C-Code
International Conference on Field-Programmable Technology (FPT), Xi'An (CN), 12-2016

A Scalable Latency-Insensitive Architecture for FPGA-Accelerated Semi-Global Matching in Stereo Vision Applications
IEEE Proc. International Conference on ReConFigurable Computing and FPGAs (ReConFig), Cancun (MX), 11-2016

Heterogeneous Wireless Sensor Nodes That Target the Internet of Things
IEEE Micro Magazine, Special Issue on Internet of Things, vol. 36, no. 6, 11-2016

C-based Synthesis of Area-Efficient Accelerators for OpenMP Worksharing Loops
Second International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC), Salt Lake City, UT (USA), 11-2016

ILP-based Modulo Scheduling for High-level Synthesis
International Conference on Compilers, Architectures and Synthesis For Embedded Systems (CASES), ESWEEK, Pittsburgh, PA (USA), 10-2016


Multi-chip dataflow architecture for massive scale biophysically accurate neuron simulation
38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), Orlando (USA), 08-2016

Automated Generation of Reconfigurable Systems-on-Chip by Interactive Code Transformations for High-Level Synthesis
Third International Workshop on FPGAs Software Programmers (FSP), Lausanne (CH), 08-2016

Third International Workshop on FPGAs for Software Programmers (FSP 2016)
Proceedings Volume, VDE Verlag, Berlin, 08-2016
Julian Oppermann, Andreas Koch
Detecting Kernels Suitable for C-based High-Level Hardware Synthesis
2nd International Workshop on Reengineering for Parallelism in Heterogeneous Parallel Platforms (RePara), IEEE ScalCom, Toulouse (FR), 07-2016

A Scalable High-Performance Hardware Architecture for Real-Time Stereo Vision by Semi-Global Matching
IEEE Conference on Computer Vision and Pattern Recognition (CVPR) Workshops, Las Vegas (USA), 06-2016


2015
Jens Huthmann, Andreas KochOptimized High-Level Synthesis of SMT Multi-Threaded Hardware Accelerators
International Conference on Field-Programmable Technology (FPT), Queenstown (NZ), 12-2015

ThreadPoolComposer – An Open-Source FPGA Toolchain for Software Developers
Second International Workshop on FPGAs Software Programmers (FSP), London (GB), 09-2015

An Open-Source Tool Flow for the Composition of Reconfigurable Hardware Thread Pool Architectures
The 23rd IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), Vancouver BC (CAN), 05-2015, (HiPEAC Paper Award)

ffLink: A Lightweight High-Performance Open-Source PCI Express Gen3 Interface for Reconfigurable Accelerators
ACM SIGARCH Computer Architecture News, Volume 43 Issue 4, 09-2015

Accelerated Clock Drift Estimation for High-Precision Wireless Time-Synchronization
IEEE Proc. Conference on Local Computer Networks (LCN), Clearwater Beach, Florida (USA), 10-2015

DEMO: The Need for Wireless Clock Drift Estimation and Its Acceleration on a Heterogeneous Sensor Node
IEEE Proc. Conference on Local Computer Networks (LCN), Clearwater Beach, Florida (USA), 10-2015

A Heterogeneous System Architecture for Low-Power Wireless Sensor Nodes in Compute-intensive Distributed Applications
IEEE Proc. Conference on Local Computer Networks (LCN), Clearwater Beach, Florida (USA), 10-2015

Domain-specific Optimisation for the High-level Synthesis of CellML-based Simulation Accelerators
IEEE Proc. Intl. Conf. on Field Programmable Logic and Applications (FPL), London (UK), 09-2015

Performance optimisation strategies for automatically generated FPGA accelerators for biomedical models
Concurrency and Computation: Practice and Experience, Wiley, Volume 28, Issue 5

2014
Andreas Engel, Paul Hildebrand, Peter P. Pott, Helmut F. Schlaak, Andreas KochHardware-Accelerated Embedded Controller for a Piezo-electric Haptic Feedback System
Proc. 14th International Conference on New Actuators and Drive Systems (ACTUATOR 2014), Bremen (DE), 06-2014

Hardware-Accelerated Data Compression in Low-Power Wireless Sensor Networks
LNCS Proc. 10th International Symposium on Applied Reconfigurable Computing (ARC), Vilamoura (PT), 04-2014

Synthilation: JIT-Compilation of Microinstruction Sequences in AMIDAR Processors
IEEE Proc. Conference on Design & Architectures for Signal & Image Processing (DASIP), Madrid (ES), 10-2014

PHAT: A TECHNOLOGY FOR PROTOTYPING PARALLEL HETEROGENEOUS ARCHITECTURES
IEEE Proc. Conference on Design & Architectures for Signal & Image Processing (DASIP), Madrid (ES), 10-2014

Automatic high-level synthesis of multi-threaded hardware accelerators
IEEE Proc. Intl. Conf. on Field Programmable Logic and Applications (FPL), Munich (DE), 09-2014

Low-Latency Double-Precision Floating-Point Division for FPGAs
IEEE Proc. Intl. Conf. on Field-Programmable Technology (FPT), Shanghai (CN), 12-2014

Integrating FPGA-based Processing Elements into a Runtime for Parallel Heterogeneous Computing
IEEE Proc. Intl. Conf. on Field-Programmable Technology (FPT), Shanghai (CN), 12-2014

Hardware-Accelerated Wireless Sensor Network for Distributed Structural Health Monitoring
Elsevier Procedia Technology, Volume 15, 2014, Pages 738-747

An Energy-Efficient Wireless Routing Protocol for Distributed Structural Health Monitoring
IEEE Proc. 7th IFIP Wireless and Mobile Networking Conference,Vilamoura (PT), 05-2014

A Reconfigurable Platform and Programming Tools for High-Level Network Applications Demonstrated as a Hardware Honeypot
IEEE Journal on Selected Areas in Communications, 32(10): 1919-1932 (2014)

2013
Florian Stock, Dietmar Hildenbrand, Andreas KochFPGA-accelerated color edge detection using a Geometric-Algebra-to-Verilog compiler
International Symposium on System on Chip (SoC) 2013, Tampere, Finland


Liebig, B., Huthmann, J., Koch, A.
Architecture Exploration of High-Performance Floating-Point Fused Multiply-Add
Reconfigurable Architectures Workshop, Mai 2013.

Huthmann, J., Liebig, B., Oppermann, J., Koch, A.
Hardware/software co-compilation with the Nymble system
in Proc. of the Intl. Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), Darmstadt, 2013

2012
Thielmann, B., Huthmann, J., Koch, A.Memory Latency Hiding by Load Value Speculation for Reconfigurable Computers
ACM Transactions on Reconfigurable Technology and Systems, Vol. 5, No. 3, Article 13, to appear 10-2012

Engel, A., Liebig, B., Koch, A.
Energy-efficient Heterogeneous Reconfigurable Sensor Node for Distributed Structural Health Monitoring
IEEE Proc. Conference on Design & Architectures for Signal & Image Processing, 10-2012

Engel, A., Liebig, B., Koch, A.
HaLOEWEn: A Heterogeneous Reconfigurable Sensor Node for Distributed Structural Health Monitoring
IEEE Proc. Conference on Design & Architectures for Signal & Image Processing, 10-2012

Muehlbach, S., Koch, A.
Malacoda: Towards High-Level Compilation of Network Security Applications on Reconfigurable Hardware
ACM/IEEE Proc. Symposium on Architectures for Networking and Communications Systems, 10-2012

Thielmann, B., Huthmann, J., Koch, A.
Widening the Memory Bottleneck by Automatically-Compiled Application-Specific Speculation Mechanisms
in Embedded Systems Design with FPGAs by Athanas, P., Pnevmatikatos, D., Sklavos, N. (Eds)., Springer, to appear 11-2012

Mühlbach, S., Koch, A.
A Dynamically Reconfigured Network Platform for High-Speed Malware Collection
International Journal of Reconfigurable Computing, Hindawi Publishing, 01-2012

2011
Mühlbach, S., Koch, A.A Reconfigurable Hardware Platform for Secure and Efficient Malware Collection in Next-Generation High-Speed Networks
International Journal for Information Security Research, Vol. 1, Issue 4, Infonomics Society, 12-2011

Thielmann, B., Huthmann, J., Wink, T., Koch, A.
RAP: More Efficient Memory Access in Highly Speculative Execution on Reconfigurable Adaptive Computers
IEEE Proc. International Conference on ReConFigurable Computing and FPGAs (ReConFig), Cancun (MX), 11-2011

Thielmann, B., Huthmann, J., Koch, A.
PreCoRe -- A Token-based Speculation Architecture For High-Level Language to Hardware Compilation
IEEE Proc. Intl. Conf. on Field Programmable Logic and Applications (FPL), Chania (GR), 09-2011

Janda, O., Liebig, B., Lange, H., Konigorski, U., Koch, A.
Design and Hardware Implementation of a Controller for Active Damping of a Smart Structure
Proc. 14th Intl. Adaptronic Congress, Darmstadt (D), 09-2011

Thielmann, B., Huthmann, J., Koch, A.
Evaluation of Speculative Execution Techniques for High-Level Language to Hardware Compilation
IEEE Proc. 6th Intl. Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), Montpellier (F), 06-2011.

Mühlbach, S., Koch, A.
A Scalable Multi-FPGA Platform for Complex Networking Applications
IEEE 19th Annual Symposium on Field-Programmable Custom Computing Machines (FCCM), Napa (USA), 05-2011.

Lange, H.
Reconfigurable Computing Platforms and Target System Architectures for Automatic HW/SW Compilation (Dissertation/Doctoral Thesis)
TU Darmstadt (Germany) 2011

Feasibility Analysis of Reconfigurable Computing in Low-Power Wireless Sensor Applications
LNCS Proc. 7th International Symposium on Applied Reconfigurable Computing (ARC), Belfast (UK), 03-2011

NetStage/DPR: A Self-Adaptable FPGA Platform for Application-Level Network Security
LNCS Proc. 7th International Symposium on Applied Reconfigurable Computing (ARC), Belfast (UK), 03-2011

Reconfigurable Computing: Architectures, Tools and Applications
Lecture Notes in Computer Science 6578, Springer (D), 03-2011 Lange, H., Wink, T., Koch, A.
MARC II: A Parametrized Speculative Multi-Ported Memory Subsystem for Reconfigurable Computers
ACM Proc. Design, Automation, and Test in Europe (DATE), Grenoble (F), 03-2011

Mühlbach, S., Koch, A.
A Novel Network Platform for Secure and Efficient Malware Collection based on Reconfigurable Hardware Logic
IEEE Proc. World Congress on Internet Security (WorldCIS), London (UK), 02-2011

2010
Huthmann, J., Müller, P., Stock, F., Hildenbrand, D., Koch, A.Compiling Geometric Algebra Computations into Reconfigurable Hardware Accelerators
Dagstuhl Seminar Proc. #10281 on Dynamically Reconfigurable Architectures, 12-2010

Mühlbach, S., Koch, A.
A Dynamically Reconfigured Network Platform for High-Speed Malware Collection
IEEE Proc. Intl. Conf. on ReConFigurable Computing and FPGAs (ReConFig), Cancun (MX), 12-2010

Stöttinger, M., Huss, S., Mühlbach, S., Koch, A.
Side-Channel Resistance Evaluation of a Neural Network Based Lightweight Cryptography Scheme
IEEE Proc. Intl. Conf. on Embedded and Ubiquitous Computing (EUC), Hong Kong (CH), 12-2010

Mühlbach, S., Koch, A.
An FPGA-based Scalable Platform for High-Speed Malware Collection in Large IP Networks
IEEE Proc. Intl. Conf. on Field-Programmable Technology (FPT), Beijing (CH), 12-2010

Lange, H., Koch, A.
Architectures and Execution Models for Hardware/Software Compilation and their System-Level Realization
IEEE Transactions on Computers pp. 1363-1377, IEEE Computer Society Digital Library, 10-2010

A Comparison of Hardware Acceleration Interfaces in a Customizable Soft Core Processor
IEEE Proc. Intl. Conf. on Field Programmable Logic and Applications (FPL), Milano (IT), 08-2010

Mühlbach, S., Brunner, M., Roblee, C., Koch, A.
MalCoBox: Designing a 10 Gb/s Malware Collection Honeypot Using Reconfigurable Technology
IEEE Proc. Intl. Conf. on Field Programmable Logic and Applications (FPL), Milano (IT), 08-2010

Gädke-Lütjens, H., Thielmann, B., Koch, A.
A Flexible Compute and Memory Infrastructure for High-Level Language to Hardware Compilation
IEEE Intl. Conf. on Field Programmable Logic and Applications (FPL), Milano (I), 08-2010.




Gaalop 2.0 - A Geometric Algebra Algorithm Compiler
Proc. Workshop on Computer Graphics, Computer Vision and Mathematics (GraVisMa)_, Brno (CZ), 07-2010

Huthmann, J., Müller, P., Stock, F., Hildenbrand, D., Koch, A.
Accelerating High-Level Engineering Computations by Automatic Compilation of Geometric Algebra to Hardware Accelerators
IEEE Proc. Intl. Conf. on Embedded Computer Systems: Architectures, MOdeling and Simulation (SAMOS), Samos (GR), 07-2010

Hildenbrand, D., Pitt, J., Koch, A.
High Performance Geometric Algebra Computing based on Gaalop
in American Journal of Mathematics: Geometric Algebra Computing for Engineering and Computer Science, by Eduardo Bayro-Corrochano and Gerik Scheuermann (Eds.), Springer, 05-2010.

Adaptive Computing Systems and their Design Tools
in Dynamically Reconfigurable Systems by Platzner, M.; Teich, J.; Wehn, N. (Eds.), Springer, 2010

2009
Hochberger, C., Koch, A.Challenges of Electronic CAD in the Nano Scale Era
GI LNI Workshop Grand Challenges der technischen Informatik, Lübeck (Germany), 10-2009

A Fast GPU Implementation for Solving Sparse Ill-Posed Linear Equation Systems
LNCS Proc. of Eighth International Conference on Parallel Processing and Mathematics
Minisymposium on GPU Computing, Wroclaw (Poland), 09-2009

A Novel Processor Architecture for McEliece Cryptosystem and FPGA Platforms
IEEE 20th International Conference on Application-specific Systems, Architectures and Processors (ASAP), Boston (MA, USA), 07-2009

Acceleration and Energy Efficiency of a Geometric Algebra Computation using Reconfigurable Computers and GPUs
IEEE Seventeenth Annual Symposium on Field-Programmable Custom Computing Machines (FCCM), Napa (USA), 04-2009.

2008
Lange, H., Koch, A.Low-Latency High-Bandwidth HW/SW Communication in a Virtual Memory Environment
IEEE Intl. Conf. on Field Programmable Logic and Applications (FPL), Heidelberg (D), 09-2008.

Memory Access Parallelization in High-Level Language Compilation for Reconfigurable Adaptive Computers
IEEE Intl. Conf. on Field Programmable Logic and Applications (FPL), Heidelberg (D), 09-2008.

Rekonfigurierbare Architekturen
GI Informatik Spektrum, Band 31, Heft 4, 08-2008 Gädke, H., Koch, A.
Accelerating Speculative Execution in High-Level Synthesis with Cancel Tokens
LNCS Intl. Workshop on Applied Reconfigurable Computing, London (UK), 03-2008.

Proceedings of the 9th Workshop on Parallel Systems and Algorithms (PASA)
GI Lecture Notes in Informatics No. 124, 02-2008 Hildenbrand, D., Lange, H., Stock, F., Koch, A.
Efficient Inverse Kinematics Algorithm based on Conformal Geometric Algebra Using Reconfigurable Hardware
Intl. Conf. on Computer Graphics Theory and Applications (GRAPP), Funchal (PT), 01-2008.

Datapath Composition
in Reconfigurable Computing, by Hauck S. and DeHon A. (Eds.), Morgan Kaufmann, 01-2008.
2007
Gädke, H., Koch, A.Comrade - A Compiler for Adaptive Computing Systems Using a Novel Fast Speculation Technique
IEEE Intl. Conf. on Field Programmable Logic and Applications (FPL), Amsterdam (NL), 08-2007.

An Execution Model for Hardware/Software Compilation and its System-Level Realization
IEEE Intl. Conf. on Field Programmable Logic and Applications (FPL), Amsterdam (NL), 08-2007.

Comrade - A Compiler for Adaptive Systems
Design, Automation and Test in Europe (DATE), Conference & Exhibition, Nizza (F), 04-2007.

ARCS '07 - 20th International Conference on Architecture of Computing Systems 2007
Workshop Proceedings, VDE Verlag, 03-2007. Lange, H., Koch, A.
Design and System Level Evaluation of a High Performance Memory System for reconfigurable SoC Platforms
Proc. HiPEAC Workshop on Reconfigurable Computing, Gent, 01-2007

Efficient Integration of Pipelined IP Blocks into Automatically Compiled Datapaths
EURASIP Journal on Embedded Systems, 2007 Special Issue on Dynamically Reconfigurable Systems.

2006
Koch, A., Leong, P., Boemo, E.Proceedings of the 2006 International Conference on Field-Programmable Logic and Applications
IEEE, 2006 Stock, F., Koch, A.
Architecture Exploration and Tools for Pipelined Coarse-grained Reconfigurable Arrays
IEEE Intl. Conf. On Field-Programmable Logic (FPL), Madrid (E), 09-2006.

2005
Kasprzyk, N., van der Veen, J.C., Koch, A.Configuration Merging for Adaptive Computer Applications
IEEE Intl. Conf. On Field-Programmable Logic (FPL), Tampere (FI), 09-2005.

High-Level-Language Compilation for Reconfigurable Computers
Intl. Conf. on Reconfigurable Communication-centric SoCs, Montpellier (F), 06-2005.

2004
Koch, A.Advances in Adaptive Computer Technology
Tech. Univ. Braunschweig, Germany, 12-2004.

Verbesserte Hardware-Software-Partitionierung für Adaptive Computer
GI Architecture of Computing Systems (ARCS): Workshop on Dynamically Reconfigurable Systems, Augsburg, 03-2004.

Architecture-Independent Meta-Optimization by Aggressive Tail Splitting
LNCS Euro-Par Conference, Pisa, 08-2004.

Wavelet-based Image Compression on the Reconfigurable Computer ACE-V
LNCS Intl. Conf. On Field-Programmable Logic (FPL), Antwerpen, 09-2004.

Hardware/Software-Codesign by Automatic Embedding of Complex IP Cores
LNCS Intl. Conf. On Field-Programmable Logic (FPL), Antwerpen, 09-2004.

2003
Schmidt, C., Koch, A.Fast Region Labeling on the Reconfigurable Platform ACE-V
LNCS Workshop on Field Programmable Logic and Applications, Lissabon, 09-2003.

Compilation for Adaptive Computers: Experiences and Opportunities
IBFI-Seminar Dynamically Reconfigurable Architectures, Dagstuhl, 07-2003.

An Improved Intermediate Representation for Datapath Generation
International Conference on Engineering of Reconfigurable Systems and Algorithms, Las Vegas, 06-2003.

Tutorial: Reconfigurable Computing - Fundamentals, Architectures, and Tools
Conference on Design Automation and Test in Europe (DATE), München, 03-2003.

Eine effiziente Kontrollfluss-Repräsentation für die Erzeugung von Datenpfaden
11. E.I.S. Workshop, Erlangen, 03-2003.

2002
Koch, A., Kasprzyk, N.Module Generators Driving the Compilation for Adaptive Computing Systems
IEEE International Symposium on FCCMs, Napa Valley, CA, USA, 04-2002. Koch, A.
Architectures and Tools for Heterogeneous Reconfigurable Systems
IEEE Workshop on Heterogeneous Reconfigurable Systems-on-Chip, Hamburg, 04-2002.

Compilation for Adaptive Computing Systems Using Complex Parameterized Hardware Objects
Kluwer Journal of Supercomputing 21, p. 179-190, 2002.

2001
Neumann, T., Koch, A.A Generic Library for Adaptive Computing Environments
LNCS Workshop on Field-Programmable Logic and Applications, Belfast, 08-2001.

Advances in Compiler Construction for Adaptive Computers
International Conference on Parallel and Distributed Processing Techniques and Applications, Las Vegas, 06-2001.

Adaptive Rechensysteme und ihre Entwurfswerkzeuge
10. E.I.S.-Workshop, Dresden, 04-2001.

2000
Lange, H., Koch, A.Memory Access Schemes for Configurable Processors
LNCS Intl. Workshop on Field-Programmable Logic and Applications, Villach, 08-2000.

Creation and Embedding of Complex Parameterized Hardware Objects
LNCS Workshop on Engineering of Reconfigurable Hardware/Software Objects, Las Vegas, 06-2000.

A Comprehensive Prototyping Platform for Hardware-Software Codesign
IEEE Workshop on Rapid Systems Prototyping, Paris, 06-2000.

1999
Koch, A.Adaptive Rechensysteme - Architekturen und Werkzeuge.
9. E.I.S.-Workshop, Darmstadt, 09-1999.

On Tool Integration in High-Performance FPGA Design Flows
LNCS Intl. Workshop on Field-Programmable Logic and Applications, Glasgow (Scotland), 09-1999.

A Processor for Artificial Life Simulation
LNCS Intl. Workshop on Field-Programmable Logic and Applications, Glasgow (Scotland), 09-1999.

Enabling Automatic Module Generation for FCCM Compilers
IEEE Intl. Symposium on FCCMs, Napa Valley (CA, USA), 04-1999.

Unified Access to Heterogeneous Module Generators
ACM Intl. Symposium on FPGAs, Monterey (CA, USA), 02-1999.
1998
Koch, A.Generator-based Design Flows for Reconfigurable Computing: A Tutorial on Tool Integration using FLAME
PACT98 Workshop on Reconfigurable Computing, Paris, 10-1998.

Accessing Module Libraries (Talk)
ACS Principal Investigator Conference, Napa Valley (CA, USA), 04-1998. Koch, A.
Proposal for inter-tool communication protocols in the ACS/NC System (Talk)
Synopsys Inc., Mountain View (CA, USA), 04-1998. Koch, A.
Efficient Datapath Composition for Coarse-Grained FPGAs (Talk)
Xilinx Inc., San Jose (CA, USA), 04-1998. Koch, A.
FLAME - A Flexible API for Module-based Environments (Talk)
2nd ACS Project Review, Berkeley (CA, USA), 03-1998.

Regular Datapaths on Field-Programmable Gate Arrays (Talk)
3rd BRASS/IRAM Industrial Feedback Retreat, Granlibakken (NV, USA), 01-1998.

1997
Koch, A.Practical Experiences with the SPARXIL Co-Processor
IEEE 31st Asilomar Conference on Signals, Systems, and Computers, Pacific Grove (CA), 1997.

Regular Datapaths on Field-Programmable Gate Arrays (Dissertation/Doctoral Thesis)
Tech. Univ. Braunschweig (Germany) 1997.

Objekt-orientierte Modellierung von hybriden Hardware- Software-Systemen am Beispiel des "European Home System" (EHS) Standards.
Proc. 8. E.I.S. Workshop, Hamburg 1997

1996
Koch, A.Module Compaction in FPGA-based Regular Datapaths
ACM Proc. 33rd Design Automation Conference (DAC), Las Vegas 1996.

Structured Design Implementation - A Strategy for Implementing Regular Datapaths on FPGAs
ACM Proc. 4th International Symposium on FPGAs (FPGA), Monterey 1996.

1995
Koch, A.Effiziente Implementierung von Datenpfaden auf FPGAs
Proc. 7. E.I.S. Workshop, Chemnitz 1995.

Structured Design Implementation - Eine Implementierungsstrategie für Datenpfade auf FPGAs
Proc. GI/ITG Workshop "Anwenderprogrammierbare Schaltungen", Karlsruhe 1995.

1994
Koch, A.A Universal Co-Processor for Workstations
in "More FPGAs'', Hrsg. Moore, W., Luk, W., Oxford 1994.

User-friendly FPGA Design with an Improved Cadence Opus - Xilinx XACT Interface
Proc. 5th EUROCHIP Workshop, Dresden 1994.

SPARXIL: Ein konfigurierbarer FPGA-Coprozessor
Proc. GI/ITG Workshop "Arch. für hochintegrierte Schaltungen'', Schloß Dagstuhl 1994.

1993
Koch, A.An FPGA-based Co-Processor for SBus Workstations
LNCS Proc. 3rd Conference on Field Programmable Logic and Applications (FPL), Oxford 1993.

FPGA Applications in Education and Research
Proc. 4th EUROCHIP Workshop, p. 260-265, Toledo 1993.

1992
Koch, A.Experiences with the Framework Cadence Skill/IL
Proc. 3rd EUROCHIP Workshop, p. 118-123, Grenoble 1992.

Integrationssprachen in VLSI-Design-Frameworks am Beispiel von Cadence Skill/IL
Diplomarbeit, Tech. Univ. Braunschweig (Germany) 1992.